87 lines
2.3 KiB
YAML
87 lines
2.3 KiB
YAML
# Copyright (c) 2019 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Properties defining the interface for the Nordic QSPI peripheral.
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The reg property describes two register blocks: one for the memory
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corresponding to the QSPI peripheral registers, and another for
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the memory mapped XIP area:
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qspi: qspi@2b000 {
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compatible = "nordic,nrf-qspi";
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reg = <0x2b000 0x1000>, <0x10000000 0x10000000>;
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reg-names = "qspi", "qspi_mm";
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...
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};
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Above, the register block with base address 0x2b000 and name
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"qspi" are the QSPI peripheral registers. The register block with
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base address 0x10000000 and name "qspi_mm" is the XIP area.
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compatible: "nordic,nrf-qspi"
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include: [flash-controller.yaml, pinctrl-device.yaml]
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bus: qspi
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properties:
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"#address-cells":
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required: true
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const: 1
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"#size-cells":
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required: true
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const: 0
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interrupts:
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required: true
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sck-pin:
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type: int
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deprecated: true
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required: false
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description: |
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IMPORTANT: This option will only be used if the new pin control driver
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is not enabled.
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The SCK pin to use.
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For pins P0.0 through P0.31, use the pin number. For example,
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to use P0.16 for SCK, set:
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sck-pin = <16>;
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For pins P1.0 through P1.31, add 32 to the pin number. For
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example, to use P1.2 for SCK, set:
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sck-pin = <34>; /* 32 + 2 */
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io-pins:
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type: array
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required: false
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description: |
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IMPORTANT: This option will only be used if the new pin control driver
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is not enabled.
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Pin numbers associated with IO0 through IO3 signals.
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Examples:
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io-pins = <io0-pin io1-pin>; // two pins
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io-pins = <io0-pin io1-pin io2-pin io3-pin>; // four pins
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Either two or four pins must be configured using this property
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as shown above. The pin numbering scheme is the same as the
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sck-pin property's.
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csn-pins:
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type: array
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required: false
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description: |
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IMPORTANT: This option will only be used if the new pin control driver
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is not enabled.
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Chip select signal pin number. Exactly one pin should be
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given. The pin numbering scheme is the same as the
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sck-pin property's.
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