68 lines
1.3 KiB
YAML
68 lines
1.3 KiB
YAML
# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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include: base.yaml
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description: |
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LiteX Mixed Mode Clock Manager clock output binding
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compatible: "litex,clkout"
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properties:
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"#clock-cells":
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required: true
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type: int
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description: |
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Number of cells in a clock specifier;
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Typically 0 for nodes with a single clock output
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and 1 for nodes with multiple clock outputs.
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const: 1
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clock-output-names:
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required: true
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type: string
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description: |
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string of clock output signal name.
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litex,clock-frequency:
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required: true
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type: int
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description: |
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default frequency in Hz for clock output
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litex,clock-phase:
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required: true
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type: int
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description: |
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default phase offset given in degrees
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litex,clock-duty-num:
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required: true
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type: int
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description: |
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default duty cycle numerator value
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litex,clock-duty-den:
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required: true
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type: int
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description: |
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default duty cycle denominator value
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litex,clock-margin:
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required: true
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type: int
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description: |
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clock output margin coefficient
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litex,clock-margin-exp:
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required: true
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type: int
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description: |
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exponent for clkout margin
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effective clkout margin shall be
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margin * 10^(-exponent) * 100%
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clock-cells:
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- id
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