107 lines
2.2 KiB
Plaintext
107 lines
2.2 KiB
Plaintext
/*
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* Copyright 2020 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <freq.h>
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#include <arm64/armv8-a.dtsi>
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#include <zephyr/dt-bindings/clock/imx_ccm.h>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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zephyr,console = &uart2;
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zephyr,shell-uart = &uart2;
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zephyr,sram = &sram0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <1>;
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};
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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gic: interrupt-controller@38800000 {
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compatible = "arm,gic";
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reg = <0x38800000 0x10000>, /* GIC Dist */
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<0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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};
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soc {
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ana_pll: ana_pll@30360000 {
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compatible = "nxp,imx-ana";
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reg = <0x30360000 DT_SIZE_K(64)>;
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label = "ANA_PLL";
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};
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ccm: ccm@30380000 {
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compatible = "nxp,imx-ccm";
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reg = <0x30380000 DT_SIZE_K(64)>;
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label = "CCM";
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#clock-cells = <3>;
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};
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uart2: uart@30890000 {
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compatible = "nxp,imx-iuart";
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reg = <0x30890000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL 0>;
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interrupt-names = "irq_0";
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interrupt-parent = <&gic>;
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label = "UART_2";
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status = "disabled";
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};
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uart4: uart@30a60000 {
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compatible = "nxp,imx-iuart";
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reg = <0x30a60000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL 0>;
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interrupt-names = "irq_0";
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interrupt-parent = <&gic>;
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label = "UART_4";
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status = "disabled";
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};
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iomuxc: iomuxc@30330000 {
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compatible = "nxp,imx-iomuxc";
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reg = <0x30330000 DT_SIZE_K(64)>;
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status = "okay";
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pinctrl: pinctrl {
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status = "okay";
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compatible = "nxp,imx8mp-pinctrl";
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};
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};
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};
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};
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