293 lines
7.5 KiB
Plaintext
293 lines
7.5 KiB
Plaintext
/*
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* Copyright (c) 2019 Lexmark International, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv7-r.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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#include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
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/ {
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soc {
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flash0: flash@c0000000 {
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compatible = "soc-nv-flash";
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reg = <0xc0000000 DT_SIZE_M(32)>;
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};
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sram0: memory@0 {
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compatible = "mmio-sram";
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reg = <0 DT_SIZE_M(64)>;
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};
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ocm: memory@fffc0000 {
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compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
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reg = <0xfffc0000 DT_SIZE_K(256)>;
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zephyr,memory-region = "OCM";
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};
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uart0: uart@ff000000 {
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compatible = "xlnx,xuartps";
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reg = <0xff000000 0x4c>;
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status = "disabled";
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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label = "UART_0";
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};
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uart1: uart@ff010000 {
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compatible = "xlnx,xuartps";
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reg = <0xff010000 0x4c>;
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status = "disabled";
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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label = "UART_1";
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};
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ttc0: timer@ff110000 {
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compatible = "xlnx,ttcps";
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status = "disabled";
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0", "irq_1", "irq_2";
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reg = <0xff110000 0x1000>;
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label = "ttc0";
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};
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ttc1: timer@ff120000 {
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compatible = "xlnx,ttcps";
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status = "disabled";
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0", "irq_1", "irq_2";
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reg = <0xff120000 0x1000>;
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label = "ttc1";
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};
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ttc2: timer@ff130000 {
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compatible = "xlnx,ttcps";
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status = "disabled";
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0", "irq_1", "irq_2";
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reg = <0xff130000 0x1000>;
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label = "ttc2";
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};
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ttc3: timer@ff140000 {
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compatible = "xlnx,ttcps";
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status = "disabled";
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0", "irq_1", "irq_2";
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reg = <0xff140000 0x1000>;
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label = "ttc3";
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};
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gem0: ethernet@ff0b0000 {
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compatible = "xlnx,gem";
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reg = <0xff0b0000 0x1000>,
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<0xff5e0050 0x4>;
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status = "disabled";
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0", "irq_1";
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label = "gem0";
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mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>;
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phy-poll-interval = <1000>;
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link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>;
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amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>;
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amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>;
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hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>;
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hw-rx-buffer-offset = <0>;
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hw-tx-buffer-size-full;
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rx-buffer-descriptors = <32>;
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tx-buffer-descriptors = <32>;
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rx-buffer-size = <512>;
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tx-buffer-size = <512>;
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discard-rx-fcs;
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unicast-hash;
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full-duplex;
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};
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gem1: ethernet@ff0c0000 {
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compatible = "xlnx,gem";
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reg = <0xff0c0000 0x1000>,
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<0xff5e0054 0x4>;
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status = "disabled";
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0", "irq_1";
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label = "gem1";
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mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>;
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phy-poll-interval = <1000>;
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link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>;
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amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>;
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amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>;
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hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>;
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hw-rx-buffer-offset = <0>;
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hw-tx-buffer-size-full;
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rx-buffer-descriptors = <32>;
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tx-buffer-descriptors = <32>;
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rx-buffer-size = <512>;
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tx-buffer-size = <512>;
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discard-rx-fcs;
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unicast-hash;
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full-duplex;
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};
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gem2: ethernet@ff0d0000 {
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compatible = "xlnx,gem";
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reg = <0xff0d0000 0x1000>,
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<0xff5e0058 0x4>;
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status = "disabled";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 62 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0", "irq_1";
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label = "gem2";
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mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>;
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phy-poll-interval = <1000>;
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link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>;
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amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>;
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amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>;
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hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>;
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hw-rx-buffer-offset = <0>;
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hw-tx-buffer-size-full;
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rx-buffer-descriptors = <32>;
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tx-buffer-descriptors = <32>;
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rx-buffer-size = <512>;
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tx-buffer-size = <512>;
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discard-rx-fcs;
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unicast-hash;
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full-duplex;
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};
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gem3: ethernet@ff0e0000 {
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compatible = "xlnx,gem";
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reg = <0xff0e0000 0x1000>,
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<0xff5e005c 0x4>;
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status = "disabled";
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 64 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0", "irq_1";
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label = "gem3";
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mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>;
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phy-poll-interval = <1000>;
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link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>;
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amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>;
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amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>;
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hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>;
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hw-rx-buffer-offset = <0>;
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hw-tx-buffer-size-full;
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rx-buffer-descriptors = <32>;
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tx-buffer-descriptors = <32>;
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rx-buffer-size = <512>;
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tx-buffer-size = <512>;
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discard-rx-fcs;
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unicast-hash;
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full-duplex;
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};
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psgpio: gpio@ff0a0000 {
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compatible = "xlnx,ps-gpio";
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status = "disabled";
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reg = <0xff0a0000 0x1000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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label = "psgpio";
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ranges;
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#address-cells = <1>;
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#size-cells = <0>;
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psgpio_bank0: psgpio_bank@0 {
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compatible = "xlnx,ps-gpio-bank";
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reg = <0x0>;
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label = "psgpio_bank0_mio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <26>;
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status = "okay";
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};
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psgpio_bank1: psgpio_bank@1 {
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compatible = "xlnx,ps-gpio-bank";
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reg = <0x1>;
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label = "psgpio_bank1_mio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <26>;
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status = "okay";
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};
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psgpio_bank2: psgpio_bank@2 {
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compatible = "xlnx,ps-gpio-bank";
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reg = <0x2>;
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label = "psgpio_bank2_mio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <26>;
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status = "okay";
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};
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psgpio_bank3: psgpio_bank@3 {
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compatible = "xlnx,ps-gpio-bank";
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reg = <0x3>;
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label = "psgpio_bank3_emio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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status = "okay";
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};
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psgpio_bank4: psgpio_bank@4 {
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compatible = "xlnx,ps-gpio-bank";
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reg = <0x4>;
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label = "psgpio_bank4_emio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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status = "okay";
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};
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psgpio_bank5: psgpio_bank@5 {
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compatible = "xlnx,ps-gpio-bank";
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reg = <0x5>;
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label = "psgpio_bank5_emio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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status = "okay";
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};
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};
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};
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};
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