197 lines
4.8 KiB
Plaintext
197 lines
4.8 KiB
Plaintext
/*
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* Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv7-a.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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#include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
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/ {
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soc {
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interrupt-parent = <&gic>;
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ocm_low: memory@1000 {
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compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
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reg = <0x00001000 DT_SIZE_K(188)>;
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zephyr,memory-region = "OCM_LOW";
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};
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ocm_high: memory@fffc0000 {
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compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
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reg = <0xFFFC0000 DT_SIZE_K(256)>;
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zephyr,memory-region = "OCM_HIGH";
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};
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arch_timer: timer@f8f00200 {
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compatible = "arm,armv8-timer";
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status = "okay";
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interrupt-names = "irq_0", "irq_1", "irq_2", "irq_3";
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interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_EDGE
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_EDGE
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_EDGE
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IRQ_DEFAULT_PRIORITY>;
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reg = <0xf8f00200 0x1C>;
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};
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gic: interrupt-controller@f8f01000 {
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compatible = "arm,gic";
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status = "okay";
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reg = <0xf8f01000 0x1000>,
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<0xf8f00100 0x100>;
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interrupt-controller;
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#interrupt-cells = <4>;
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label = "gic";
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};
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gem0: ethernet@e000b000 {
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compatible = "xlnx,gem";
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status = "disabled";
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reg = <0xe000b000 0x1000>,
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<0xf8000140 0x4>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 23 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0", "irq_1";
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label = "gem0";
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mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>;
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phy-poll-interval = <1000>;
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link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>;
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amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>;
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amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>;
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hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>;
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hw-rx-buffer-offset = <0>;
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hw-tx-buffer-size-full;
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rx-buffer-descriptors = <32>;
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tx-buffer-descriptors = <32>;
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rx-buffer-size = <512>;
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tx-buffer-size = <512>;
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discard-rx-fcs;
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unicast-hash;
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full-duplex;
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};
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gem1: ethernet@e000c000 {
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compatible = "xlnx,gem";
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status = "disabled";
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reg = <0xe000c000 0x1000>,
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<0xf8000144 0x4>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0", "irq_1";
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label = "gem1";
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mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>;
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phy-poll-interval = <1000>;
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link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>;
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amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>;
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amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>;
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hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>;
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hw-rx-buffer-offset = <0>;
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hw-tx-buffer-size-full;
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rx-buffer-descriptors = <32>;
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tx-buffer-descriptors = <32>;
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rx-buffer-size = <512>;
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tx-buffer-size = <512>;
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discard-rx-fcs;
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unicast-hash;
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full-duplex;
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};
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uart0: uart@e0000000 {
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compatible = "xlnx,xuartps";
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status = "disabled";
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reg = <0xe0000000 0x4c>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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label = "uart0";
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};
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uart1: uart@e0001000 {
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compatible = "xlnx,xuartps";
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status = "disabled";
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reg = <0xe0001000 0x4c>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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label = "uart1";
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};
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psgpio: gpio@e000a000 {
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compatible = "xlnx,ps-gpio";
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status = "disabled";
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reg = <0xe000a000 0x1000>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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label = "psgpio";
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ranges;
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#address-cells = <1>;
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#size-cells = <0>;
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psgpio_bank0: psgpio_bank@0 {
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compatible = "xlnx,ps-gpio-bank";
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reg = <0x0>;
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label = "psgpio_bank0_mio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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status = "okay";
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};
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psgpio_bank1: psgpio_bank@1 {
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compatible = "xlnx,ps-gpio-bank";
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reg = <0x1>;
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label = "psgpio_bank1_mio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <22>;
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status = "okay";
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};
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psgpio_bank2: psgpio_bank@2 {
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compatible = "xlnx,ps-gpio-bank";
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reg = <0x2>;
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label = "psgpio_bank2_emio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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status = "okay";
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};
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psgpio_bank3: psgpio_bank@3 {
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compatible = "xlnx,ps-gpio-bank";
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reg = <0x3>;
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label = "psgpio_bank3_emio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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status = "okay";
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};
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};
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};
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slcr: slcr@f8000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,zynq-slcr", "syscon";
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reg = <0xf8000000 0x1000>;
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ranges;
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pinctrl0: pinctrl@700 {
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compatible = "xlnx,pinctrl-zynq";
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reg = <0x700 0x200>;
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syscon = <&slcr>;
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};
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};
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};
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