55 lines
1.6 KiB
C
55 lines
1.6 KiB
C
/*
|
|
* Copyright (c) 2020 Linaro Limited
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
#ifndef DMA_ATMEL_SAME70_H_
|
|
#define DMA_ATMEL_SAME70_H_
|
|
|
|
/** Peripheral Hardware Request Line Identifier */
|
|
#define DMA_PERID_HSMCI_TX_RX 0
|
|
#define DMA_PERID_SPI0_TX 1
|
|
#define DMA_PERID_SPI0_RX 2
|
|
#define DMA_PERID_SPI1_TX 3
|
|
#define DMA_PERID_SPI1_RX 4
|
|
#define DMA_PERID_QSPI_TX 5
|
|
#define DMA_PERID_QSPI_RX 6
|
|
#define DMA_PERID_USART0_TX 7
|
|
#define DMA_PERID_USART0_RX 8
|
|
#define DMA_PERID_USART1_TX 9
|
|
#define DMA_PERID_USART1_RX 10
|
|
#define DMA_PERID_USART2_TX 11
|
|
#define DMA_PERID_USART2_RX 12
|
|
#define DMA_PERID_PWM0_TX 13
|
|
#define DMA_PERID_TWIHS0_TX 14
|
|
#define DMA_PERID_TWIHS0_RX 15
|
|
#define DMA_PERID_TWIHS1_TX 16
|
|
#define DMA_PERID_TWIHS1_RX 17
|
|
#define DMA_PERID_TWIHS2_TX 18
|
|
#define DMA_PERID_TWIHS2_RX 19
|
|
#define DMA_PERID_UART0_TX 20
|
|
#define DMA_PERID_UART0_RX 21
|
|
#define DMA_PERID_UART1_TX 22
|
|
#define DMA_PERID_UART1_RX 23
|
|
#define DMA_PERID_UART2_TX 24
|
|
#define DMA_PERID_UART2_RX 25
|
|
#define DMA_PERID_UART3_TX 26
|
|
#define DMA_PERID_UART3_RX 27
|
|
#define DMA_PERID_UART4_TX 28
|
|
#define DMA_PERID_UART4_RX 29
|
|
#define DMA_PERID_DACC_TX 30
|
|
#define DMA_PERID_SSC_TX 32
|
|
#define DMA_PERID_SSC_RX 33
|
|
#define DMA_PERID_PIOA_RX 34
|
|
#define DMA_PERID_AFEC0_RX 35
|
|
#define DMA_PERID_AFEC1_RX 36
|
|
#define DMA_PERID_AES_TX 37
|
|
#define DMA_PERID_AES_RX 38
|
|
#define DMA_PERID_PWM1_TX 39
|
|
#define DMA_PERID_TC0_RX 40
|
|
#define DMA_PERID_TC1_RX 41
|
|
#define DMA_PERID_TC2_RX 42
|
|
#define DMA_PERID_TC3_RX 43
|
|
|
|
#endif /* DMA_ATMEL_SAME70_H_ */
|