zephyr/arch/xtensa/core
Lauren Murphy 318e6db239 debug: coredump: add xtensa intel adsp, support toolchains
Adds compatibility with Intel ADSP GDB from Zephyr SDK and
from Cadence toolchain to coredump_gdbserver.py.

Adds CAVS 15-25 (APL) register definitions. Implements
handle_register_single_read_packet to serve ADSP GDB
p packets.

Prevents BSA from changing between stack dump printout
and coredump by taking lock. Observed to be necessary for
accurate results on slower simulated platforms.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2022-06-23 15:44:45 -04:00
..
include
offsets
startup
CMakeLists.txt arch/xtensa: Add CCOUNT-based timing API 2022-06-07 19:04:42 +02:00
README-WINDOWS.rst
coredump.c debug: coredump: add xtensa intel adsp, support toolchains 2022-06-23 15:44:45 -04:00
cpu_idle.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
crt1.S
debug_helpers_asm.S
fatal.c debug: coredump: add xtensa intel adsp, support toolchains 2022-06-23 15:44:45 -04:00
gdbstub.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
gen_zsr.py arch/xtensa: Rework irq_offload: automatic config, SMP-safe 2022-02-21 22:10:03 -05:00
irq_manage.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
irq_offload.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
timing.c arch/xtensa: Add CCOUNT-based timing API 2022-06-07 19:04:42 +02:00
tls.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
window_vectors.S arch/xtensa: Use ZSR assignments for the alloca exception 2022-01-20 12:58:00 -05:00
xcc_stubs.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
xtensa-asm2-util.S arch: xtensa: implement ARCH_EXCEPT 2022-06-23 15:44:45 -04:00
xtensa-asm2.c arch: xtensa: implement ARCH_EXCEPT 2022-06-23 15:44:45 -04:00
xtensa_backtrace.c include: add more missing zephyr/ prefixes 2022-05-27 15:20:27 -07:00
xtensa_intgen.py include: add zephyr/ on script generated #include 2022-05-27 15:20:27 -07:00
xtensa_intgen.tmpl