zephyr/arch/riscv/core
Nicolas Pitre 83de5b4532 riscv: _isr_wrapper: get rid of the ASSUME_EQUAL() macro
This is really useful only for one case i.e. when testing against zero.
Do that test inline where it is needed and make the rest of the code
independent from the actual numerical value being tested to make code
maintenance easier if/when new cases are added.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2022-07-04 09:49:16 +02:00
..
offsets riscv: stop preserving the tp register needlessly 2022-06-23 13:12:05 -04:00
CMakeLists.txt
asm_macros.inc riscv: abstract RV32E register access 2022-06-23 13:12:05 -04:00
coredump.c riscv: Introduce support for RV32E 2022-06-08 18:50:22 +09:00
cpu_idle.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
fatal.c riscv: stop preserving the tp register needlessly 2022-06-23 13:12:05 -04:00
irq_manage.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
irq_offload.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
isr.S riscv: _isr_wrapper: get rid of the ASSUME_EQUAL() macro 2022-07-04 09:49:16 +02:00
pmp.S asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
pmp.c riscv: pmp: properly initialize per-thread m-mode/u-mode entry array 2022-06-23 15:56:00 -05:00
prep_c.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
reboot.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
reset.S asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
semihost.c
smp.c riscv: new TLS-based arch_is_user_context() implementation 2022-06-23 13:12:05 -04:00
switch.S riscv: stop preserving the tp register needlessly 2022-06-23 13:12:05 -04:00
thread.c riscv: new TLS-based arch_is_user_context() implementation 2022-06-23 13:12:05 -04:00
tls.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
userspace.S asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00