45 lines
2.4 KiB
C
45 lines
2.4 KiB
C
/* This file is a temporary workaround for mapping of the generated information
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* to the current driver definitions. This will be removed when the drivers
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* are modified to handle the generated information, or the mapping of
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* generated data matches the driver definitions.
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*/
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_I2C_0_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWI_4008C000_BASE_ADDRESS
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#define CONFIG_I2C_0_NAME DT_ATMEL_SAM_I2C_TWI_4008C000_LABEL
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#define DT_I2C_0_BITRATE DT_ATMEL_SAM_I2C_TWI_4008C000_CLOCK_FREQUENCY
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#define DT_I2C_0_IRQ DT_ATMEL_SAM_I2C_TWI_4008C000_IRQ_0
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#define DT_I2C_0_IRQ_PRI DT_ATMEL_SAM_I2C_TWI_4008C000_IRQ_0_PRIORITY
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#define DT_I2C_0_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWI_4008C000_PERIPHERAL_ID
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#define DT_I2C_1_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWI_40090000_BASE_ADDRESS
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#define CONFIG_I2C_1_NAME DT_ATMEL_SAM_I2C_TWI_40090000_LABEL
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#define DT_I2C_1_BITRATE DT_ATMEL_SAM_I2C_TWI_40090000_CLOCK_FREQUENCY
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#define DT_I2C_1_IRQ DT_ATMEL_SAM_I2C_TWI_40090000_IRQ_0
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#define DT_I2C_1_IRQ_PRI DT_ATMEL_SAM_I2C_TWI_40090000_IRQ_0_PRIORITY
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#define DT_I2C_1_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWI_40090000_PERIPHERAL_ID
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#define DT_UART_SAM_PORT_0_NAME DT_ATMEL_SAM_UART_400E0800_LABEL
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#define DT_UART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_UART_400E0800_CURRENT_SPEED
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#define DT_UART_SAM_PORT_0_IRQ DT_ATMEL_SAM_UART_400E0800_IRQ_0
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#define DT_UART_SAM_PORT_0_IRQ_PRIO DT_ATMEL_SAM_UART_400E0800_IRQ_0_PRIORITY
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#define DT_USART_SAM_PORT_0_NAME DT_ATMEL_SAM_USART_40098000_LABEL
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#define DT_USART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_USART_40098000_CURRENT_SPEED
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#define DT_USART_SAM_PORT_1_NAME DT_ATMEL_SAM_USART_4009C000_LABEL
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#define DT_USART_SAM_PORT_1_BAUD_RATE DT_ATMEL_SAM_USART_4009C000_CURRENT_SPEED
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#define DT_USART_SAM_PORT_2_NAME DT_ATMEL_SAM_USART_400A0000_LABEL
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#define DT_USART_SAM_PORT_2_BAUD_RATE DT_ATMEL_SAM_USART_400A0000_CURRENT_SPEED
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#define DT_USART_SAM_PORT_3_NAME DT_ATMEL_SAM_USART_400A4000_LABEL
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#define DT_USART_SAM_PORT_3_BAUD_RATE DT_ATMEL_SAM_USART_400A4000_CURRENT_SPEED
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#define DT_WDT_SAM_IRQ DT_ATMEL_SAM_WATCHDOG_400E1A50_IRQ_0
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#define DT_WDT_SAM_IRQ_PRIORITY DT_ATMEL_SAM_WATCHDOG_400E1A50_IRQ_0_PRIORITY
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#define DT_WDT_SAM_LABEL DT_ATMEL_SAM_WATCHDOG_400E1A50_LABEL
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#define DT_WDT_SAM_BASE_ADDRESS DT_ATMEL_SAM_WATCHDOG_400E1A50_BASE_ADDRESS
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#define CONFIG_WDT_0_NAME DT_WDT_SAM_LABEL
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/* End of SoC Level DTS fixup file */
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