203 lines
5.0 KiB
Plaintext
203 lines
5.0 KiB
Plaintext
# ARC EM4 options
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#
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# Copyright (c) 2014 Wind River Systems, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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menu "ARC Options"
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depends on ARC
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config ARCH
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default "arc"
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menu "ARC EM4 processor options"
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config CPU_ARCEM4
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bool
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default y
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select CPU_ARCV2
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select ATOMIC_OPERATIONS_C
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help
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This option signifies the use of an ARC EM4 CPU
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endmenu
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menu "ARCv2 Family Options"
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config CPU_ARCV2
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bool
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select ARCH_HAS_STACK_PROTECTION if ARC_HAS_STACK_CHECKING || ARC_MPU
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select ARCH_HAS_USERSPACE if ARC_MPU
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default y
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help
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This option signifies the use of a CPU of the ARCv2 family.
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config DATA_ENDIANNESS_LITTLE
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bool
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default y
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help
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This is driven by the processor implementation, since it is fixed in
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hardware. The BSP should set this value to 'n' if the data is
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implemented as big endian.
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config NUM_IRQ_PRIO_LEVELS
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int "Number of supported interrupt priority levels"
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range 1 16
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help
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Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1.
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The minimum value is 1.
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The BSP must provide a valid default for proper operation.
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config NUM_IRQS
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int "Upper limit of interrupt numbers/IDs used"
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range 17 256
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help
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Interrupts available will be 0 to NUM_IRQS-1.
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The minimum value is 17 as the first 16 entries in the vector
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table are for CPU exceptions.
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The BSP must provide a valid default. This drives the size of the
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vector table.
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config RGF_NUM_BANKS
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int "Number of General Purpose Register Banks"
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depends on CPU_ARCV2
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range 1 2
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default 2
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help
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The ARC CPU can be configured to have more than one register
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bank. If fast interrupts are supported (FIRQ), the 2nd
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register bank, in the set, will be used by FIRQ interrupts.
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If fast interrupts are supported but there is only 1
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register bank, the fast interrupt handler must save
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and restore general purpose registers.
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config ARC_FIRQ
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bool "FIRQ enable"
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default y
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help
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Fast interrupts are supported (FIRQ). If FIRQ enabled, for interrupts
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with highest priority, status32 and pc will be saved in aux regs,
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other regs will be saved according to the number of register bank;
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If FIRQ is disabled, the handle of interrupts with highest priority
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will be same with other interrupts.
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config ARC_HAS_STACK_CHECKING
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bool "ARC has STACK_CHECKING"
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default y
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help
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ARC is configured with STACK_CHECKING which is a mechanism for
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checking stack accesses and raising an exception when a stack
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overflow or underflow is detected.
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config ARC_STACK_CHECKING
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bool
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help
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Use ARC STACK_CHECKING to do stack protection
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config ARC_STACK_PROTECTION
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bool
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default y if HW_STACK_PROTECTION
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select ARC_STACK_CHECKING if ARC_HAS_STACK_CHECKING
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select MPU_STACK_GUARD if (!ARC_STACK_CHECKING && ARC_MPU)
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select THREAD_STACK_INFO
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help
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This option enables either:
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- The ARC stack checking, or
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- the MPU-based stack guard
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to cause a system fatal error
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if the bounds of the current process stack are overflowed.
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The two stack guard options are mutually exclusive. The
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selection of the ARC stack checking is
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prioritized over the MPU-based stack guard.
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config FAULT_DUMP
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int "Fault dump level"
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default 2
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range 0 2
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help
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Different levels for display information when a fault occurs.
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2: The default. Display specific and verbose information. Consumes
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the most memory (long strings).
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1: Display general and short information. Consumes less memory
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(short strings).
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0: Off.
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config XIP
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default y if !UART_NSIM
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config GEN_ISR_TABLES
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default y
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config GEN_IRQ_START_VECTOR
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default 16
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config HARVARD
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bool "Harvard Architecture"
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help
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The ARC CPU can be configured to have two busses;
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one for instruction fetching and another that serves as a data bus.
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config CODE_DENSITY
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bool "Code Density Option"
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help
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Enable code density option to get better code density
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config ARC_HAS_SECURE
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bool
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# a hidden option
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help
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This option is enabled when ARC core supports secure mode
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menu "ARC MPU Options"
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depends on CPU_HAS_MPU
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config ARC_MPU_ENABLE
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bool "Enable MPU"
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select ARC_MPU
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help
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Enable MPU
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source "arch/arc/core/mpu/Kconfig"
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endmenu
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config CACHE_LINE_SIZE_DETECT
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bool "Detect d-cache line size at runtime"
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help
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This option enables querying the d-cache build register for finding
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the d-cache line size at the expense of taking more memory and code
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and a slightly increased boot time.
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If the CPU's d-cache line size is known in advance, disable this
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option and manually enter the value for CACHE_LINE_SIZE.
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config CACHE_LINE_SIZE
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int "Cache line size" if !CACHE_LINE_SIZE_DETECT
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default 32
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help
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Size in bytes of a CPU d-cache line.
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Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.
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config ARCH_CACHE_FLUSH_DETECT
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bool
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config CACHE_FLUSHING
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bool "Enable d-cache flushing mechanism"
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help
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This links in the sys_cache_flush() function, which provides a
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way to flush multiple lines of the d-cache.
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If the d-cache is present, set this to y.
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If the d-cache is NOT present, set this to n.
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endmenu
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endmenu
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