90 lines
1.8 KiB
Plaintext
90 lines
1.8 KiB
Plaintext
/*
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* Copyright 2020 NXP
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* Copyright 2022 HNU-ESNL
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* Copyright 2022 openEuler SIG-Zephyr
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm64/armv8-a.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "rockchip,rk3568";
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@000 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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enable-method = "psci";
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reg = <0x000>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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enable-method = "psci";
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reg = <0x100>;
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};
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cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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enable-method = "psci";
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reg = <0x200>;
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};
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cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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enable-method = "psci";
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reg = <0x300>;
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};
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};
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gic: interrupt-controller@fd400000 {
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#address-cells = <1>;
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compatible = "arm,gic-v3","arm,gic";
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#interrupt-cells = <4>;
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interrupt-controller;
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reg = <0xfd400000 0x10000>, /* GICD */
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<0xfd460000 0xc0000>; /* GICR */
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status = "okay";
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};
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psci {
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compatible = "arm,psci-0.2", "arm,psci";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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uart2: serial@fe660000 {
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compatible = "rockchip,rk3568-uart", "ns16550";
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reg = <0xfe660000 0x10000>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
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clock-frequency = <12000000>;
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reg-shift = <2>;
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status = "disabled";
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};
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};
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