343 lines
8.6 KiB
C
343 lines
8.6 KiB
C
/*
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* Copyright (c) 2022 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/init.h>
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#include <errno.h>
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#include <zephyr/crypto/crypto.h>
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#include "crypto_intel_sha_priv.h"
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(SHA);
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#define DT_DRV_COMPAT intel_adsp_sha
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static struct sha_session sha_sessions[SHA_MAX_SESSIONS];
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static int intel_sha_get_unused_session_idx(void)
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{
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int i;
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for (i = 0; i < SHA_MAX_SESSIONS; i++) {
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if (!sha_sessions[i].in_use) {
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sha_sessions[i].in_use = true;
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return i;
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}
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}
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return -1;
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}
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static int intel_sha_set_ctl_enable(struct sha_container *sha, int status)
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{
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/* wait until not busy when turning off */
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if (status == 0 && sha->dfsha->shactl.part.en == 1) {
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while (sha->dfsha->shasts.part.busy) {
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}
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}
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sha->dfsha->shactl.part.en = status;
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return 0;
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}
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static int intel_sha_set_resume_length_dw0(struct sha_container *sha, uint32_t lower_length)
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{
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int err = -EINVAL;
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if (IS_ALIGNED(lower_length, SHA_REQUIRED_BLOCK_ALIGNMENT)) {
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sha->dfsha->sharldw0.full = lower_length;
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err = 0;
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}
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return err;
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}
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static int intel_sha_set_resume_length_dw1(struct sha_container *sha, uint32_t upper_length)
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{
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sha->dfsha->sharldw1.full = upper_length;
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return 0;
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}
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static int intel_sha_regs_cpy(void *dst, const void *src, size_t len)
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{
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uint32_t counter;
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int err = -EINVAL;
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if ((IS_ALIGNED(len, sizeof(uint32_t))) && (IS_ALIGNED(dst, sizeof(uint32_t))) &&
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(IS_ALIGNED(src, sizeof(uint32_t)))) {
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len /= sizeof(uint32_t);
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for (counter = 0; counter != len; ++counter) {
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((uint32_t *)dst)[counter] = ((uint32_t *)src)[counter];
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}
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err = 0;
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}
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return err;
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}
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/* ! Perform SHA computation over requested region. */
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static int intel_sha_device_run(const struct device *dev, const void *buf_in, size_t buf_in_size,
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size_t max_buff_len, uint32_t state)
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{
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int err;
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struct sha_container *const self = dev->data;
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union sha_state state_u = { .full = state };
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/* align to OWORD */
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const size_t aligned_buff_size = ROUND_UP(buf_in_size, 0x10);
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err = intel_sha_set_ctl_enable(self, 0);
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if (err) {
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return err;
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}
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/* set processing element disable */
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self->dfsha->pibcs.part.peen = 0;
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/* set pib base addr */
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self->dfsha->pibba.full = (uint32_t)buf_in;
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if (max_buff_len < aligned_buff_size) {
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return -EINVAL;
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}
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self->dfsha->pibs.full = aligned_buff_size;
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/* enable interrupt */
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self->dfsha->pibcs.part.bscie = 1;
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self->dfsha->pibcs.part.teie = 0;
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/* set processing element enable */
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self->dfsha->pibcs.part.peen = 1;
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if (self->dfsha->shactl.part.en) {
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return -EINVAL; /* already enabled */
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}
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self->dfsha->shactl.part.hrsm = state_u.part.hrsm;
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/* set initial values if resuming */
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if (state_u.part.hrsm) {
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err = intel_sha_set_resume_length_dw0(self, self->dfsha->shaaldw0.full);
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if (err) {
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return err;
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}
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err = intel_sha_set_resume_length_dw1(self, self->dfsha->shaaldw1.full);
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if (err) {
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return err;
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}
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err = intel_sha_regs_cpy((void *)self->dfsha->initial_vector,
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(void *)self->dfsha->sha_result,
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sizeof(self->dfsha->initial_vector));
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if (err) {
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return err;
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}
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}
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/* set ctl hash first middle */
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if (self->dfsha->shactl.part.en) {
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return -EINVAL; /* already enabled */
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}
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self->dfsha->shactl.part.hfm = state_u.part.state;
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/* increment pointer */
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self->dfsha->pibfpi.full = buf_in_size;
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err = intel_sha_set_ctl_enable(self, 1);
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if (err) {
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return err;
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}
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err = intel_sha_set_ctl_enable(self, 0);
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return err;
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}
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static int intel_sha_copy_hash(struct sha_container *const self, void *dst, size_t len)
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{
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/* NOTE: generated hash value should be read from the end */
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int err = -EINVAL;
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uint32_t counter = 0;
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uint32_t last_idx = 0;
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if ((IS_ALIGNED(len, sizeof(uint32_t))) && (IS_ALIGNED(dst, sizeof(uint32_t)))) {
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len /= sizeof(uint32_t);
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counter = 0;
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/* The index of a last element in the sha result buffer. */
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last_idx = (sizeof(self->dfsha->sha_result) / sizeof(uint32_t)) - 1;
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for (counter = 0; counter != len; counter++) {
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((uint32_t *)dst)[counter] =
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((uint32_t *)self->dfsha->sha_result)[last_idx - counter];
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}
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err = 0;
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}
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return err;
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}
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static int intel_sha_device_get_hash(const struct device *dev, void *buf_out, size_t buf_out_size)
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{
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int err;
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struct sha_container *const self = dev->data;
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if (buf_out == NULL) {
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return -EINVAL;
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}
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/* wait until not busy */
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while (self->dfsha->shasts.part.busy) {
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}
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err = intel_sha_copy_hash(self, buf_out, buf_out_size);
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return err;
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}
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static int intel_sha_compute(struct hash_ctx *ctx, struct hash_pkt *pkt, bool finish)
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{
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int ret;
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struct sha_container *self = (struct sha_container *const)(ctx->device)->data;
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struct sha_session *session = (struct sha_session *)ctx->drv_sessn_state;
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size_t frag_length;
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size_t output_size;
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uint32_t *hash_int_ptr = (uint32_t *)(pkt->out_buf);
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/* set algo */
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self->dfsha->shactl.full = 0x0;
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self->dfsha->shactl.part.algo = session->algo;
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/* restore ctx */
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self->dfsha->shaaldw0 = session->sha_ctx.shaaldw0;
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self->dfsha->shaaldw1 = session->sha_ctx.shaaldw1;
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ret = intel_sha_regs_cpy((void *)self->dfsha->initial_vector,
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(void *)session->sha_ctx.initial_vector,
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sizeof(self->dfsha->initial_vector));
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if (ret) {
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return ret;
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}
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ret = intel_sha_regs_cpy((void *)self->dfsha->sha_result,
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(void *)session->sha_ctx.sha_result,
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sizeof(self->dfsha->sha_result));
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if (ret) {
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return ret;
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}
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/* compute hash */
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do {
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frag_length = pkt->in_len > SHA_API_MAX_FRAG_LEN ?
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SHA_API_MAX_FRAG_LEN :
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pkt->in_len;
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if ((frag_length == pkt->in_len) && finish) {
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session->state.part.state = SHA_LAST;
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}
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ret = intel_sha_device_run(ctx->device, pkt->in_buf, frag_length, frag_length,
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session->state.full);
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if (ret) {
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return ret;
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}
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/* set state for next iteration */
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session->state.part.hrsm = SHA_HRSM_ENABLE;
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session->state.part.state = SHA_MIDLE;
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pkt->in_len -= frag_length;
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pkt->in_buf += frag_length;
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} while (pkt->in_len > 0);
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if (finish) {
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switch (self->dfsha->shactl.part.algo) {
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case CRYPTO_HASH_ALGO_SHA224:
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output_size = SHA224_ALGORITHM_HASH_SIZEOF;
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break;
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case CRYPTO_HASH_ALGO_SHA256:
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output_size = SHA256_ALGORITHM_HASH_SIZEOF;
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break;
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case CRYPTO_HASH_ALGO_SHA384:
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output_size = SHA384_ALGORITHM_HASH_SIZEOF;
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break;
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case CRYPTO_HASH_ALGO_SHA512:
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output_size = SHA512_ALGORITHM_HASH_SIZEOF;
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break;
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default:
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return -ENOTSUP;
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}
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ret = intel_sha_device_get_hash(ctx->device, pkt->out_buf, output_size);
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if (ret) {
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return ret;
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}
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/* Fix byte ordering to match common hash representation. */
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for (size_t i = 0; i != output_size / sizeof(uint32_t); i++) {
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hash_int_ptr[i] = BYTE_SWAP32(hash_int_ptr[i]);
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}
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}
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return ret;
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}
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static int intel_sha_device_set_hash_type(const struct device *dev, struct hash_ctx *ctx,
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enum hash_algo algo)
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{
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int ctx_idx;
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struct sha_container *self = (struct sha_container *const)(dev)->data;
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ctx_idx = intel_sha_get_unused_session_idx();
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if (ctx_idx < 0) {
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LOG_ERR("All sessions in use!");
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return -ENOSPC;
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}
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ctx->drv_sessn_state = &sha_sessions[ctx_idx];
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/* set processing element enable */
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self->dfsha->pibcs.part.peen = 0;
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/* populate sha session data */
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sha_sessions[ctx_idx].state.part.state = SHA_FIRST;
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sha_sessions[ctx_idx].state.part.hrsm = SHA_HRSM_DISABLE;
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sha_sessions[ctx_idx].algo = algo;
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ctx->hash_hndlr = intel_sha_compute;
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return 0;
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}
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static int intel_sha_device_free(const struct device *dev, struct hash_ctx *ctx)
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{
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struct sha_container *self = (struct sha_container *const)(dev)->data;
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struct sha_session *session = (struct sha_session *)ctx->drv_sessn_state;
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(void)memset((void *)self->dfsha, 0, sizeof(struct sha_hw_regs));
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(void)memset(&session->sha_ctx, 0, sizeof(struct sha_context));
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(void)memset(&session->state, 0, sizeof(union sha_state));
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session->in_use = 0;
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session->algo = 0;
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return 0;
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}
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static int intel_sha_device_hw_caps(const struct device *dev)
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{
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return (CAP_SEPARATE_IO_BUFS | CAP_SYNC_OPS);
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}
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static struct crypto_driver_api hash_enc_funcs = {
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.hash_begin_session = intel_sha_device_set_hash_type,
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.hash_free_session = intel_sha_device_free,
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.hash_async_callback_set = NULL,
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.query_hw_caps = intel_sha_device_hw_caps,
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};
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#define INTEL_SHA_DEVICE_INIT(inst) \
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static struct sha_container sha_data_##inst = { \
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.dfsha = (volatile struct sha_hw_regs *)DT_INST_REG_ADDR_BY_IDX(inst, 0) \
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}; \
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DEVICE_DT_INST_DEFINE(inst, NULL, NULL, &sha_data_##inst, NULL, \
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POST_KERNEL, CONFIG_CRYPTO_INIT_PRIORITY, (void *)&hash_enc_funcs);
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DT_INST_FOREACH_STATUS_OKAY(INTEL_SHA_DEVICE_INIT)
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