101 lines
3.1 KiB
Plaintext
101 lines
3.1 KiB
Plaintext
# Kconfig - XTENSA architecture configuration options
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#
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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menu "XTENSA Options"
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depends on XTENSA
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menu "Specific core configuration"
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config IRQ_OFFLOAD_INTNUM
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int "IRQ offload SW interrupt index"
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help
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The index of the software interrupt to be used for IRQ offload.
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Please note that in order for IRQ offload to work correctly the selected
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interrupt shall have its priority shall not exceed XCHAL_EXCM_LEVEL.
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config XTENSA_OMIT_HIGH_INTERRUPTS
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bool "Skip generation of vectors for high priority interrupts"
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help
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Setting this to y causes the interrupt vectors for "high
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priority" Xtensa interrupts (those not masked by the EXCM bit
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in PS) to be left ungenerated, so they can be handled by
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application code instead. Note that high priority interrupts
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cannot safely be handled by C code anyway (they will interrupt
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register window exceptions, which cannot be made reentrant, so
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the code under the handler must not emit them), though some
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devices might still want to use built-in handling for things
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like watchdogs which do not need to return into interrupted
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code. Default is "n" for legacy compatibility. Consider
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changing to "y" in the future.
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config XTENSA_ASM2
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bool "New-style Xtensa context switch & interrupt layer"
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select USE_SWITCH
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select USE_SWITCH_SUPPORTED
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help
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This selects a new implementation of context switching and
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interrupt handling. Advantages are a much lower interrupt
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overhead and smaller code size, and this scheme is required
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for SMP. Assumes/requires hardware that implements the
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register window extension, however.
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endmenu
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config ARCH
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default "xtensa"
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config SIMULATOR_XTENSA
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bool "Simulator Configuration"
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help
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Specify if the board configuration should be treated as a simulator.
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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int "Hardware clock cycles per second, 2000000 for ISS"
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default 2000000
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range 1000000 1000000000
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help
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This option specifies hardware clock.
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config XTENSA_NO_IPC
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bool "Core has no IPC support"
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select ATOMIC_OPERATIONS_C
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help
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Uncheck this if you core does not implement "SCOMPARE1" register and "s32c1i"
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instruction.
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config SW_ISR_TABLE
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bool "Enable software interrupt handler table"
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default y
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help
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Enable an interrupt handler table implemented in software. This
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table, unlike ISRs connected directly in the vector table, allow
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a parameter to be passed to the interrupt handlers. Also, invoking
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the exception/interrupt exit stub is automatically done.
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config XTENSA_RESET_VECTOR
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bool "Build reset vector code"
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default y
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help
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This option controls whether the initial reset vector code is built.
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This is always needed for the simulator. Real boards may already
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implement this in boot ROM.
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config XTENSA_USE_CORE_CRT1
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bool "Use crt1.S from core"
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default y
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help
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SoC or boards might define their own __start by setting this setting
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to false.
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config XTENSA_KERNEL_CPU_PTR_SR
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string
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default "MISC0"
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help
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Specify which special register to store the pointer to
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_kernel.cpus[] for the current CPU.
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endmenu
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