516 lines
14 KiB
C
516 lines
14 KiB
C
/* adc_dw.c - Designware ADC driver */
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/*
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* Copyright (c) 2015 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <errno.h>
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#include <init.h>
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#include <kernel.h>
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#include <string.h>
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#include <stdlib.h>
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#include <board.h>
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#include <adc.h>
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#include <arch/cpu.h>
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#include "adc_dw.h"
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#define ADC_CLOCK_GATE (1 << 31)
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#define ADC_POWER_DOWN 0x01
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#define ADC_STANDBY 0x02
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#define ADC_NORMAL_WITH_CALIB 0x03
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#define ADC_NORMAL_WO_CALIB 0x04
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#define ADC_MODE_MASK 0x07
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#define ONE_BIT_SET 0x1
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#define THREE_BITS_SET 0x7
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#define FIVE_BITS_SET 0x1f
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#define SIX_BITS_SET 0x3f
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#define SEVEN_BITS_SET 0xef
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#define ELEVEN_BITS_SET 0x7ff
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#define INPUT_MODE_POS 5
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#define CAPTURE_MODE_POS 6
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#define OUTPUT_MODE_POS 7
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#define SERIAL_DELAY_POS 8
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#define SEQUENCE_MODE_POS 13
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#define SEQ_ENTRIES_POS 16
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#define THRESHOLD_POS 24
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#define SEQ_DELAY_EVEN_POS 5
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#define SEQ_MUX_ODD_POS 16
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#define SEQ_DELAY_ODD_POS 21
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#ifdef CONFIG_SOC_QUARK_SE_C1000_SS
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#define int_unmask(__mask) \
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sys_write32(sys_read32((__mask)) & ENABLE_SSS_INTERRUPTS, (__mask))
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#else
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#define int_unmask(...) { ; }
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#endif
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static void adc_config_irq(void);
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#ifdef CONFIG_ADC_DW_CALIBRATION
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static void calibration_command(uint8_t command)
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{
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uint32_t state;
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uint32_t reg_value;
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state = irq_lock();
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reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_MST0);
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reg_value |= (command & THREE_BITS_SET) << 17;
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reg_value |= 0x10000;
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sys_out32(reg_value, PERIPH_ADDR_BASE_CREG_MST0);
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irq_unlock(state);
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/*Poll waiting for command*/
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do {
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reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_SLV0);
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} while ((reg_value & 0x10) == 0);
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/*Clear Calibration Request*/
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reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_MST0);
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reg_value &= ~(0x10000);
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sys_out32(reg_value, PERIPH_ADDR_BASE_CREG_MST0);
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}
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static void adc_goto_normal_mode(struct device *dev)
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{
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struct adc_info *info = dev->driver_data;
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uint8_t calibration_value;
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uint32_t reg_value;
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uint32_t state;
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reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_SLV0);
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if (((reg_value & 0xE) >> 1) != ADC_NORMAL_WITH_CALIB) {
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state = irq_lock();
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/*Request Normal With Calibration Mode*/
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reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_MST0);
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reg_value &= ~(ADC_MODE_MASK);
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reg_value |= ADC_NORMAL_WITH_CALIB;
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sys_out32(reg_value, PERIPH_ADDR_BASE_CREG_MST0);
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irq_unlock(state);
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/*Poll waiting for normal mode*/
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do {
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reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_SLV0);
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} while ((reg_value & 0x1) == 0);
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if (info->calibration_value == ADC_NONE_CALIBRATION) {
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/*Reset Calibration*/
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calibration_command(ADC_CMD_RESET_CALIBRATION);
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/*Request Calibration*/
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calibration_command(ADC_CMD_START_CALIBRATION);
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reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_SLV0);
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calibration_value = (reg_value >> 5) & SEVEN_BITS_SET;
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info->calibration_value = calibration_value;
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}
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/*Load Calibration*/
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reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_MST0);
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reg_value |= (info->calibration_value << 20);
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sys_out32(reg_value, PERIPH_ADDR_BASE_CREG_MST0);
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calibration_command(ADC_CMD_LOAD_CALIBRATION);
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}
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}
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#else
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static void adc_goto_normal_mode(struct device *dev)
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{
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uint32_t reg_value;
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uint32_t state;
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ARG_UNUSED(dev);
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reg_value = sys_in32(
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PERIPH_ADDR_BASE_CREG_SLV0 + SLV_OBSR);
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if (((reg_value & 0xE) >> 1) == ADC_NORMAL_WO_CALIB) {
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state = irq_lock();
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/*Request Power Down*/
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reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_MST0);
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reg_value &= ~(ADC_MODE_MASK);
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reg_value |= ADC_POWER_DOWN;
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sys_out32(reg_value, PERIPH_ADDR_BASE_CREG_MST0);
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irq_unlock(state);
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do {
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reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_SLV0);
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} while ((reg_value & 0x1) == 0);
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}
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/*Request Normal With Calibration Mode*/
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state = irq_lock();
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reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_MST0);
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reg_value &= ~(ADC_MODE_MASK);
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reg_value |= ADC_NORMAL_WO_CALIB;
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sys_out32(reg_value, PERIPH_ADDR_BASE_CREG_MST0);
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irq_unlock(state);
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/*Poll waiting for normal mode*/
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do {
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reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_SLV0);
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} while ((reg_value & 0x1) == 0);
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}
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#endif
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static void adc_goto_deep_power_down(void)
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{
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uint32_t reg_value;
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uint32_t state;
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reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_SLV0);
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if ((reg_value & 0xE >> 1) != 0) {
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state = irq_lock();
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reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_MST0);
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reg_value &= ~(ADC_MODE_MASK);
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reg_value |= 0 | ADC_CLOCK_GATE;
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sys_out32(reg_value, PERIPH_ADDR_BASE_CREG_MST0);
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irq_unlock(state);
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do {
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reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_SLV0);
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} while ((reg_value & 0x1) == 0);
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}
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}
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static void adc_dw_enable(struct device *dev)
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{
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uint32_t reg_value;
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struct adc_info *info = dev->driver_data;
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const struct adc_config *config = dev->config->config_info;
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uint32_t adc_base = config->reg_base;
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/*Go to Normal Mode*/
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sys_out32(ADC_INT_DSB|ENABLE_ADC, adc_base + ADC_CTRL);
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adc_goto_normal_mode(dev);
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/*Clock Gate*/
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reg_value = sys_in32(PERIPH_ADDR_BASE_CREG_MST0);
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reg_value &= ~(ADC_CLOCK_GATE);
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sys_out32(reg_value, PERIPH_ADDR_BASE_CREG_MST0);
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sys_out32(ENABLE_ADC, adc_base + ADC_CTRL);
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info->state = ADC_STATE_IDLE;
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}
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static void adc_dw_disable(struct device *dev)
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{
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uint32_t saved;
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struct adc_info *info = dev->driver_data;
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const struct adc_config *config = dev->config->config_info;
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uint32_t adc_base = config->reg_base;
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sys_out32(ADC_INT_DSB|ENABLE_ADC, adc_base + ADC_CTRL);
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adc_goto_deep_power_down();
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sys_out32(ADC_INT_DSB|ADC_SEQ_PTR_RST, adc_base + ADC_CTRL);
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saved = irq_lock();
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sys_out32(sys_in32(adc_base + ADC_SET)|ADC_FLUSH_RX, adc_base + ADC_SET);
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irq_unlock(saved);
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info->state = ADC_STATE_DISABLED;
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}
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static int adc_dw_read_request(struct device *dev, struct adc_seq_table *seq_tbl)
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{
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uint32_t i;
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uint32_t ctrl;
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uint32_t tmp_val;
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uint32_t num_iters;
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uint32_t saved;
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struct adc_seq_entry *entry;
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struct adc_info *info = dev->driver_data;
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const struct adc_config *config = dev->config->config_info;
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uint32_t adc_base = config->reg_base;
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if (info->state != ADC_STATE_IDLE) {
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return 1;
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}
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saved = irq_lock();
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info->seq_size = seq_tbl->num_entries;
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ctrl = sys_in32(adc_base + ADC_CTRL);
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ctrl |= ADC_SEQ_PTR_RST;
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sys_out32(ctrl, adc_base + ADC_CTRL);
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tmp_val = sys_in32(adc_base + ADC_SET);
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tmp_val &= ADC_SEQ_SIZE_SET_MASK;
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tmp_val |= (((seq_tbl->num_entries - 1) & SIX_BITS_SET)
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<< SEQ_ENTRIES_POS);
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tmp_val |= ((seq_tbl->num_entries - 1) << THRESHOLD_POS);
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sys_out32(tmp_val, adc_base + ADC_SET);
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irq_unlock(saved);
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num_iters = seq_tbl->num_entries/2;
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for (i = 0, entry = seq_tbl->entries;
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i < num_iters; i++, entry += 2) {
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tmp_val = ((entry[1].sampling_delay & ELEVEN_BITS_SET)
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<< SEQ_DELAY_ODD_POS);
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tmp_val |= ((entry[1].channel_id & FIVE_BITS_SET)
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<< SEQ_MUX_ODD_POS);
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tmp_val |= ((entry[0].sampling_delay & ELEVEN_BITS_SET)
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<< SEQ_DELAY_EVEN_POS);
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tmp_val |= (entry[0].channel_id & FIVE_BITS_SET);
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sys_out32(tmp_val, adc_base + ADC_SEQ);
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}
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if ((seq_tbl->num_entries % 2) != 0) {
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tmp_val = ((entry[0].sampling_delay & ELEVEN_BITS_SET)
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<< SEQ_DELAY_EVEN_POS);
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tmp_val |= (entry[0].channel_id & FIVE_BITS_SET);
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sys_out32(tmp_val, adc_base + ADC_SEQ);
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}
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sys_out32(ctrl | ADC_SEQ_PTR_RST, adc_base + ADC_CTRL);
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info->entries = seq_tbl->entries;
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#ifdef CONFIG_ADC_DW_REPETITIVE
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memset(info->index, 0, seq_tbl->num_entries);
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#endif
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info->state = ADC_STATE_SAMPLING;
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sys_out32(START_ADC_SEQ, adc_base + ADC_CTRL);
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k_sem_take(&info->device_sync_sem, K_FOREVER);
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if (info->state == ADC_STATE_ERROR) {
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info->state = ADC_STATE_IDLE;
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return -EIO;
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}
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return 0;
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}
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static int adc_dw_read(struct device *dev, struct adc_seq_table *seq_tbl)
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{
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struct adc_info *info = dev->driver_data;
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#ifdef CONFIG_ADC_DW_DUMMY_CONVERSION
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if (info->dummy_conversion == ADC_NONE_DUMMY) {
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adc_dw_read_request(dev, seq_tbl);
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info->dummy_conversion = ADC_DONE_DUMMY;
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}
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#endif
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return adc_dw_read_request(dev, seq_tbl);
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}
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static struct adc_driver_api api_funcs = {
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.enable = adc_dw_enable,
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.disable = adc_dw_disable,
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.read = adc_dw_read,
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};
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int adc_dw_init(struct device *dev)
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{
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uint32_t tmp_val;
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uint32_t val;
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const struct adc_config *config = dev->config->config_info;
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uint32_t adc_base = config->reg_base;
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struct adc_info *info = dev->driver_data;
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sys_out32(ADC_INT_DSB | ADC_CLK_ENABLE, adc_base + ADC_CTRL);
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tmp_val = sys_in32(adc_base + ADC_SET);
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tmp_val &= ADC_CONFIG_SET_MASK;
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val = (config->sample_width) & FIVE_BITS_SET;
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val &= ~(1 << INPUT_MODE_POS);
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val |= ((config->capture_mode & ONE_BIT_SET) << CAPTURE_MODE_POS);
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val |= ((config->out_mode & ONE_BIT_SET) << OUTPUT_MODE_POS);
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val |= ((config->serial_dly & FIVE_BITS_SET) << SERIAL_DELAY_POS);
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val |= ((config->seq_mode & ONE_BIT_SET) << SEQUENCE_MODE_POS);
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sys_out32(tmp_val|val, adc_base + ADC_SET);
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sys_out32(config->clock_ratio & ADC_CLK_RATIO_MASK,
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adc_base + ADC_DIVSEQSTAT);
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sys_out32(ADC_INT_ENABLE & ~(ADC_CLK_ENABLE),
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adc_base + ADC_CTRL);
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config->config_func();
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k_sem_init(&info->device_sync_sem, 0, UINT_MAX);
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int_unmask(config->reg_irq_mask);
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int_unmask(config->reg_err_mask);
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return 0;
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}
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#ifdef CONFIG_ADC_DW_SINGLESHOT
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static void adc_dw_rx_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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struct device_config *dev_config = dev->config;
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const struct adc_config *config = dev_config->config_info;
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struct adc_info *info = dev->driver_data;
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uint32_t adc_base = config->reg_base;
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struct adc_seq_entry *entries = info->entries;
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uint32_t reg_val;
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uint32_t seq_index;
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for (seq_index = 0; seq_index < info->seq_size; seq_index++) {
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uint32_t *adc_buffer;
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reg_val = sys_in32(adc_base + ADC_SET);
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sys_out32(reg_val|ADC_POP_SAMPLE, adc_base + ADC_SET);
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adc_buffer = (uint32_t *)entries[seq_index].buffer;
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*adc_buffer = sys_in32(adc_base + ADC_SAMPLE);
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}
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/*Resume ADC state to continue new conversions*/
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sys_out32(RESUME_ADC_CAPTURE, adc_base + ADC_CTRL);
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reg_val = sys_in32(adc_base + ADC_SET);
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sys_out32(reg_val | ADC_FLUSH_RX, adc_base + ADC_SET);
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info->state = ADC_STATE_IDLE;
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/*Clear data A register*/
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reg_val = sys_in32(adc_base + ADC_CTRL);
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sys_out32(reg_val | ADC_CLR_DATA_A, adc_base + ADC_CTRL);
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k_sem_give(&info->device_sync_sem);
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}
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#else /*CONFIG_ADC_DW_REPETITIVE*/
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static void adc_dw_rx_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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struct device_config *dev_config = dev->config;
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const struct adc_config *config = dev_config->config_info;
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struct adc_info *info = dev->driver_data;
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uint32_t adc_base = config->reg_base;
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struct adc_seq_entry *entries = info->entries;
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uint32_t reg_val;
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uint32_t sequence_index;
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uint8_t full_buffer_flag = 0;
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for (sequence_index = 0; sequence_index < info->seq_size; sequence_index++) {
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uint32_t *adc_buffer;
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uint32_t repetitive_index;
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repetitive_index = info->index[sequence_index];
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/*API array is 8 bits array but ADC reads blocks of 32 bits with every sample.*/
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if (repetitive_index >= (entries[sequence_index].buffer_length >> 2)) {
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full_buffer_flag = 1;
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continue;
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}
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reg_val = sys_in32(adc_base + ADC_SET);
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sys_out32(reg_val|ADC_POP_SAMPLE, adc_base + ADC_SET);
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adc_buffer = (uint32_t *)entries[sequence_index].buffer;
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adc_buffer[repetitive_index] = sys_in32(adc_base + ADC_SAMPLE);
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repetitive_index++;
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info->index[sequence_index] = repetitive_index;
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}
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if (full_buffer_flag == 1) {
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/*Resume ADC state to continue new conversions*/
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sys_out32(RESUME_ADC_CAPTURE, adc_base + ADC_CTRL);
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reg_val = sys_in32(adc_base + ADC_SET);
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sys_out32(reg_val | ADC_FLUSH_RX, adc_base + ADC_SET);
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info->state = ADC_STATE_IDLE;
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/*Clear data A register*/
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reg_val = sys_in32(adc_base + ADC_CTRL);
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sys_out32(reg_val | ADC_CLR_DATA_A, adc_base + ADC_CTRL);
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k_sem_give(&info->device_sync_sem);
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return;
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}
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/*Clear data A register*/
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reg_val = sys_in32(adc_base + ADC_CTRL);
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sys_out32(reg_val | ADC_CLR_DATA_A, adc_base + ADC_CTRL);
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}
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#endif
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static void adc_dw_err_isr(void *arg)
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{
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struct device *dev = (struct device *) arg;
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const struct adc_config *config = dev->config->config_info;
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struct adc_info *info = dev->driver_data;
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uint32_t adc_base = config->reg_base;
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uint32_t reg_val = sys_in32(adc_base + ADC_SET);
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sys_out32(RESUME_ADC_CAPTURE, adc_base + ADC_CTRL);
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sys_out32(reg_val | ADC_FLUSH_RX, adc_base + ADC_CTRL);
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sys_out32(FLUSH_ADC_ERRORS, adc_base + ADC_CTRL);
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info->state = ADC_STATE_ERROR;
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k_sem_give(&info->device_sync_sem);
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}
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|
|
|
#ifdef CONFIG_ADC_DW
|
|
|
|
struct adc_info adc_info_dev = {
|
|
.state = ADC_STATE_IDLE,
|
|
#ifdef CONFIG_ADC_DW_CALIBRATION
|
|
.calibration_value = ADC_NONE_CALIBRATION,
|
|
#endif
|
|
#ifdef CONFIG_ADC_DW_DUMMY_CONVERSION
|
|
.dummy_conversion = ADC_NONE_DUMMY,
|
|
#endif
|
|
};
|
|
|
|
static struct adc_config adc_config_dev = {
|
|
.reg_base = PERIPH_ADDR_BASE_ADC,
|
|
.reg_irq_mask = SCSS_REGISTER_BASE + INT_SS_ADC_IRQ_MASK,
|
|
.reg_err_mask = SCSS_REGISTER_BASE + INT_SS_ADC_ERR_MASK,
|
|
#ifdef CONFIG_ADC_DW_SERIAL
|
|
.out_mode = 0,
|
|
#elif CONFIG_ADC_DW_PARALLEL
|
|
.out_mode = 1,
|
|
#endif
|
|
#ifdef CONFIG_ADC_DW_SINGLESHOT
|
|
.seq_mode = 0,
|
|
#elif CONFIG_ADC_DW_REPETITIVE
|
|
.seq_mode = 1,
|
|
#endif
|
|
#ifdef CONFIG_ADC_DW_RISING_EDGE
|
|
.capture_mode = 0,
|
|
#elif CONFIG_ADC_DW_FALLING_EDGE
|
|
.capture_mode = 1,
|
|
#endif
|
|
.sample_width = CONFIG_ADC_DW_SAMPLE_WIDTH,
|
|
.clock_ratio = CONFIG_ADC_DW_CLOCK_RATIO,
|
|
.serial_dly = CONFIG_ADC_DW_SERIAL_DELAY,
|
|
.config_func = adc_config_irq,
|
|
};
|
|
|
|
DEVICE_AND_API_INIT(adc_dw, CONFIG_ADC_0_NAME, &adc_dw_init,
|
|
&adc_info_dev, &adc_config_dev,
|
|
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
|
|
&api_funcs);
|
|
|
|
static void adc_config_irq(void)
|
|
{
|
|
IRQ_CONNECT(IRQ_ADC_IRQ, CONFIG_ADC_0_IRQ_PRI, adc_dw_rx_isr,
|
|
DEVICE_GET(adc_dw), 0);
|
|
irq_enable(IRQ_ADC_IRQ);
|
|
|
|
IRQ_CONNECT(IRQ_ADC_ERR, CONFIG_ADC_0_IRQ_PRI,
|
|
adc_dw_err_isr, DEVICE_GET(adc_dw), 0);
|
|
irq_enable(IRQ_ADC_ERR);
|
|
}
|
|
#endif
|