294 lines
7.0 KiB
C
294 lines
7.0 KiB
C
/*
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include <string.h>
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#include <soc/periph_defs.h>
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#include <limits.h>
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#include <assert.h>
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#include "soc/soc.h"
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#include <soc.h>
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
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#include <zephyr/sw_isr_table.h>
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#include <riscv/interrupt.h>
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#define ESP32C3_INTC_DEFAULT_PRIO 15
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(intc_esp32c3, CONFIG_LOG_DEFAULT_LEVEL);
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/*
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* Define this to debug the choices made when allocating the interrupt. This leads to much debugging
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* output within a critical region, which can lead to weird effects like e.g. the interrupt watchdog
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* being triggered, that is why it is separate from the normal LOG* scheme.
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*/
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#ifdef CONFIG_INTC_ESP32C3_DECISIONS_LOG
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# define INTC_LOG(...) LOG_INF(__VA_ARGS__)
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#else
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# define INTC_LOG(...) do {} while (0)
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#endif
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#define ESP32C3_INTC_DEFAULT_PRIORITY 15
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#define ESP32C3_INTC_DEFAULT_THRESHOLD 1
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#define ESP32C3_INTC_DISABLED_SLOT 31
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#define ESP32C3_INTC_SRCS_PER_IRQ 2
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#define ESP32C3_INTC_AVAILABLE_IRQS 30
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#if defined(CONFIG_SOC_SERIES_ESP32C6)
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#define IRQ_NA 0xFF /* IRQ not available */
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#define IRQ_FREE 0xFE
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#define ESP32C6_INTC_SRCS_PER_IRQ 2
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#define ESP32C6_INTC_AVAILABLE_IRQS 31
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/* For ESP32C6 only CPU peripheral interrupts number
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* 1, 2, 5, 6, 8 ~ 31 are available.
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* IRQ 31 is reserved for disabled interrupts
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*/
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static uint8_t esp_intr_irq_alloc[ESP32C6_INTC_AVAILABLE_IRQS][ESP32C6_INTC_SRCS_PER_IRQ] = {
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[0] = {IRQ_NA, IRQ_NA},
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[3] = {IRQ_NA, IRQ_NA},
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[4] = {IRQ_NA, IRQ_NA},
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[7] = {IRQ_NA, IRQ_NA},
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[1 ... 2] = {IRQ_FREE, IRQ_FREE},
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[5 ... 6] = {IRQ_FREE, IRQ_FREE},
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[8 ... 30] = {IRQ_FREE, IRQ_FREE}
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};
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#endif
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#define STATUS_MASK_NUM 3
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static uint32_t esp_intr_enabled_mask[STATUS_MASK_NUM] = {0, 0, 0};
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#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3)
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static uint32_t esp_intr_find_irq_for_source(uint32_t source)
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{
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/* in general case, each 2 sources goes routed to
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* 1 IRQ line.
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*/
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uint32_t irq = (source / ESP32C3_INTC_SRCS_PER_IRQ);
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if (irq > ESP32C3_INTC_AVAILABLE_IRQS) {
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INTC_LOG("Clamping the source: %d no more IRQs available", source);
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irq = ESP32C3_INTC_AVAILABLE_IRQS;
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} else if (irq == 0) {
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irq = 1;
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}
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INTC_LOG("Found IRQ: %d for source: %d", irq, source);
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return irq;
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}
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#elif defined(CONFIG_SOC_SERIES_ESP32C6)
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static uint32_t esp_intr_find_irq_for_source(uint32_t source)
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{
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uint32_t irq = IRQ_NA;
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uint32_t irq_free = IRQ_NA;
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uint8_t *irq_ptr = NULL;
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/* First allocate one source per IRQ, then two
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* if there are more sources than free IRQs
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*/
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for (int j = 0; j < ESP32C6_INTC_SRCS_PER_IRQ; j++) {
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for (int i = 0; i < ESP32C6_INTC_AVAILABLE_IRQS; i++) {
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/* Find first free slot but keep searching to see
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* if source is already associated to an IRQ
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*/
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if (esp_intr_irq_alloc[i][j] == source) {
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/* Source is already associated to an IRQ */
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irq = i;
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goto found;
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} else if ((irq_free == IRQ_NA) && (esp_intr_irq_alloc[i][j] == IRQ_FREE)) {
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irq_free = i;
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irq_ptr = &esp_intr_irq_alloc[i][j];
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}
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}
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}
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if (irq_ptr != NULL) {
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*irq_ptr = (uint8_t)source;
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irq = irq_free;
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} else {
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return IRQ_NA;
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}
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found:
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INTC_LOG("Found IRQ: %d for source: %d", irq, source);
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return irq;
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}
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#endif
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void esp_intr_initialize(void)
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{
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/* IRQ 31 is reserved for disabled interrupts,
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* so route all sources to it
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*/
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for (int i = 0 ; i < ESP32C3_INTC_AVAILABLE_IRQS + 2; i++) {
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irq_disable(i);
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}
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for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) {
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esp_rom_intr_matrix_set(0, i, ESP32C3_INTC_DISABLED_SLOT);
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}
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#if defined(CONFIG_SOC_SERIES_ESP32C6)
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/* Clear up IRQ allocation */
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for (int j = 0; j < ESP32C6_INTC_SRCS_PER_IRQ; j++) {
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for (int i = 0; i < ESP32C6_INTC_AVAILABLE_IRQS; i++) {
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/* screen out reserved IRQs */
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if (esp_intr_irq_alloc[i][j] != IRQ_NA) {
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esp_intr_irq_alloc[i][j] = IRQ_FREE;
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}
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}
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}
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#endif
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/* set global esp32c3's INTC masking level */
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esprv_intc_int_set_threshold(ESP32C3_INTC_DEFAULT_THRESHOLD);
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}
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int esp_intr_alloc(int source,
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int flags,
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isr_handler_t handler,
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void *arg,
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void **ret_handle)
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{
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ARG_UNUSED(flags);
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ARG_UNUSED(ret_handle);
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if (handler == NULL) {
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return -EINVAL;
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}
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if (source < 0 || source >= ETS_MAX_INTR_SOURCE) {
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return -EINVAL;
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}
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uint32_t key = irq_lock();
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irq_connect_dynamic(source,
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ESP32C3_INTC_DEFAULT_PRIORITY,
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handler,
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arg,
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0);
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if (source < 32) {
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esp_intr_enabled_mask[0] |= (1 << source);
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} else if (source < 64) {
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esp_intr_enabled_mask[1] |= (1 << (source - 32));
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} else if (source < 96) {
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esp_intr_enabled_mask[2] |= (1 << (source - 64));
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}
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INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X",
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esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]);
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irq_unlock(key);
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int ret = esp_intr_enable(source);
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return ret;
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}
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int esp_intr_disable(int source)
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{
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if (source < 0 || source >= ETS_MAX_INTR_SOURCE) {
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return -EINVAL;
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}
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uint32_t key = irq_lock();
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esp_rom_intr_matrix_set(0,
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source,
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ESP32C3_INTC_DISABLED_SLOT);
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#if defined(CONFIG_SOC_SERIES_ESP32C6)
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for (int j = 0; j < ESP32C6_INTC_SRCS_PER_IRQ; j++) {
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for (int i = 0; i < ESP32C6_INTC_AVAILABLE_IRQS; i++) {
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if (esp_intr_irq_alloc[i][j] == source) {
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esp_intr_irq_alloc[i][j] = IRQ_FREE;
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goto freed;
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}
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}
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}
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freed:
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#endif
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if (source < 32) {
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esp_intr_enabled_mask[0] &= ~(1 << source);
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} else if (source < 64) {
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esp_intr_enabled_mask[1] &= ~(1 << (source - 32));
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} else if (source < 96) {
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esp_intr_enabled_mask[2] &= ~(1 << (source - 64));
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}
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INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X",
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esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]);
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irq_unlock(key);
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return 0;
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}
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int esp_intr_enable(int source)
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{
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if (source < 0 || source >= ETS_MAX_INTR_SOURCE) {
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return -EINVAL;
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}
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uint32_t key = irq_lock();
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uint32_t irq = esp_intr_find_irq_for_source(source);
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#if defined(CONFIG_SOC_SERIES_ESP32C6)
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if (irq == IRQ_NA) {
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irq_unlock(key);
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return -ENOMEM;
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}
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#endif
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esp_rom_intr_matrix_set(0, source, irq);
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if (source < 32) {
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esp_intr_enabled_mask[0] |= (1 << source);
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} else if (source < 64) {
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esp_intr_enabled_mask[1] |= (1 << (source - 32));
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} else if (source < 96) {
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esp_intr_enabled_mask[2] |= (1 << (source - 64));
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}
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INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X",
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esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]);
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esprv_intc_int_set_priority(irq, ESP32C3_INTC_DEFAULT_PRIO);
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esprv_intc_int_set_type(irq, INTR_TYPE_LEVEL);
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esprv_intc_int_enable(1 << irq);
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irq_unlock(key);
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return 0;
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}
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uint32_t esp_intr_get_enabled_intmask(int status_mask_number)
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{
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INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X",
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esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]);
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if (status_mask_number < STATUS_MASK_NUM) {
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return esp_intr_enabled_mask[status_mask_number];
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} else {
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return 0; /* error */
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}
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}
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