zephyr/boards/xtensa/xt-sim
Ulf Magnusson 984bfae831 global: Remove leading/trailing blank lines in files
Remove leading/trailing blank lines in .c, .h, .py, .rst, .yml, and
.yaml files.

Will avoid failures with the new CI test in
https://github.com/zephyrproject-rtos/ci-tools/pull/112, though it only
checks changed files.

Move the 'target-notes' target in boards/xtensa/odroid_go/doc/index.rst
to get rid of the trailing blank line there. It was probably misplaced.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-12-11 19:17:27 +01:00
..
doc global: Remove leading/trailing blank lines in files 2019-12-11 19:17:27 +01:00
Kconfig.board kconfig: Clean up header comments and make them consistent 2019-11-04 17:31:27 -05:00
Kconfig.defconfig
board.cmake boards: allow cmake-time overrides of all runners 2019-06-07 13:43:51 +02:00
xt-sim.dts dts: Add information about CPU frequency to the cpu nodes 2019-07-17 21:53:36 +02:00
xt-sim.yaml
xt-sim_defconfig xtensa: kconfig: Remove unused SW_ISR_TABLE symbol 2019-10-21 16:15:41 -07:00
xt-sim_intel_s1000_defconfig xtensa: kconfig: Remove unused SW_ISR_TABLE symbol 2019-10-21 16:15:41 -07:00