314 lines
8.1 KiB
C
314 lines
8.1 KiB
C
/*
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* Copyright (c) 2018, Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/spi.h>
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#include <nrfx_spis.h>
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#define LOG_DOMAIN "spi_nrfx_spis"
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#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(spi_nrfx_spis);
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#include "spi_context.h"
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struct spi_nrfx_data {
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struct spi_context ctx;
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};
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struct spi_nrfx_config {
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nrfx_spis_t spis;
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size_t max_buf_len;
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};
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static inline struct spi_nrfx_data *get_dev_data(const struct device *dev)
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{
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return dev->data;
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}
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static inline const struct spi_nrfx_config *get_dev_config(const struct device *dev)
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{
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return dev->config;
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}
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static inline nrf_spis_mode_t get_nrf_spis_mode(uint16_t operation)
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{
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if (SPI_MODE_GET(operation) & SPI_MODE_CPOL) {
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if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
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return NRF_SPIS_MODE_3;
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} else {
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return NRF_SPIS_MODE_2;
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}
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} else {
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if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
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return NRF_SPIS_MODE_1;
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} else {
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return NRF_SPIS_MODE_0;
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}
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}
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}
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static inline nrf_spis_bit_order_t get_nrf_spis_bit_order(uint16_t operation)
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{
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if (operation & SPI_TRANSFER_LSB) {
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return NRF_SPIS_BIT_ORDER_LSB_FIRST;
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} else {
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return NRF_SPIS_BIT_ORDER_MSB_FIRST;
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}
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}
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static int configure(const struct device *dev,
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const struct spi_config *spi_cfg)
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{
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struct spi_context *ctx = &get_dev_data(dev)->ctx;
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if (spi_context_configured(ctx, spi_cfg)) {
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/* Already configured. No need to do it again. */
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return 0;
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}
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if (SPI_OP_MODE_GET(spi_cfg->operation) == SPI_OP_MODE_MASTER) {
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LOG_ERR("Master mode is not supported on %s",
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dev->name);
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return -EINVAL;
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}
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if (spi_cfg->operation & SPI_MODE_LOOP) {
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LOG_ERR("Loopback mode is not supported");
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return -EINVAL;
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}
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if ((spi_cfg->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
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LOG_ERR("Only single line mode is supported");
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return -EINVAL;
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}
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if (SPI_WORD_SIZE_GET(spi_cfg->operation) != 8) {
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LOG_ERR("Word sizes other than 8 bits"
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" are not supported");
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return -EINVAL;
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}
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if (spi_cfg->cs) {
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LOG_ERR("CS control via GPIO is not supported");
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return -EINVAL;
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}
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ctx->config = spi_cfg;
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nrf_spis_configure(get_dev_config(dev)->spis.p_reg,
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get_nrf_spis_mode(spi_cfg->operation),
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get_nrf_spis_bit_order(spi_cfg->operation));
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return 0;
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}
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static void prepare_for_transfer(const struct device *dev)
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{
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struct spi_nrfx_data *dev_data = get_dev_data(dev);
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const struct spi_nrfx_config *dev_config = get_dev_config(dev);
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struct spi_context *ctx = &dev_data->ctx;
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int status;
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size_t buf_len = spi_context_max_continuous_chunk(ctx);
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if (buf_len > 0) {
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nrfx_err_t result;
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if (buf_len > dev_config->max_buf_len) {
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buf_len = dev_config->max_buf_len;
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}
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result = nrfx_spis_buffers_set(
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&dev_config->spis,
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ctx->tx_buf,
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spi_context_tx_buf_on(ctx) ? buf_len : 0,
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ctx->rx_buf,
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spi_context_rx_buf_on(ctx) ? buf_len : 0);
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if (result == NRFX_SUCCESS) {
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return;
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}
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/* Cannot prepare for transfer. */
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status = -EIO;
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} else {
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/* Zero-length buffer provided. */
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status = 0;
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}
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spi_context_complete(ctx, status);
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}
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static int transceive(const struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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bool asynchronous,
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struct k_poll_signal *signal)
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{
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struct spi_nrfx_data *dev_data = get_dev_data(dev);
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int error;
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spi_context_lock(&dev_data->ctx, asynchronous, signal);
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error = configure(dev, spi_cfg);
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if (error != 0) {
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/* Invalid configuration. */
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} else if ((tx_bufs && tx_bufs->count > 1) ||
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(rx_bufs && rx_bufs->count > 1)) {
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LOG_ERR("Scattered buffers are not supported");
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error = -ENOTSUP;
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} else if (tx_bufs && tx_bufs->buffers[0].len &&
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!nrfx_is_in_ram(tx_bufs->buffers[0].buf)) {
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LOG_ERR("Only buffers located in RAM are supported");
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error = -ENOTSUP;
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} else {
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spi_context_buffers_setup(&dev_data->ctx, tx_bufs, rx_bufs, 1);
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prepare_for_transfer(dev);
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error = spi_context_wait_for_completion(&dev_data->ctx);
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}
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spi_context_release(&dev_data->ctx, error);
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return error;
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}
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static int spi_nrfx_transceive(const struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL);
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}
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#ifdef CONFIG_SPI_ASYNC
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static int spi_nrfx_transceive_async(const struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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struct k_poll_signal *async)
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{
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return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, async);
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}
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#endif /* CONFIG_SPI_ASYNC */
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static int spi_nrfx_release(const struct device *dev,
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const struct spi_config *spi_cfg)
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{
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struct spi_nrfx_data *dev_data = get_dev_data(dev);
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if (!spi_context_configured(&dev_data->ctx, spi_cfg)) {
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return -EINVAL;
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}
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spi_context_unlock_unconditionally(&dev_data->ctx);
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return 0;
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}
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static const struct spi_driver_api spi_nrfx_driver_api = {
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.transceive = spi_nrfx_transceive,
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#ifdef CONFIG_SPI_ASYNC
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.transceive_async = spi_nrfx_transceive_async,
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#endif
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.release = spi_nrfx_release,
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};
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static void event_handler(const nrfx_spis_evt_t *p_event, void *p_context)
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{
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struct spi_nrfx_data *dev_data = p_context;
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if (p_event->evt_type == NRFX_SPIS_XFER_DONE) {
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spi_context_complete(&dev_data->ctx, p_event->rx_amount);
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}
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}
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static int init_spis(const struct device *dev,
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const nrfx_spis_config_t *config)
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{
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struct spi_nrfx_data *dev_data = get_dev_data(dev);
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/* This sets only default values of frequency, mode and bit order.
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* The proper ones are set in configure() when a transfer is started.
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*/
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nrfx_err_t result = nrfx_spis_init(&get_dev_config(dev)->spis,
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config,
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event_handler,
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dev_data);
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if (result != NRFX_SUCCESS) {
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LOG_ERR("Failed to initialize device: %s", dev->name);
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return -EBUSY;
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}
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spi_context_unlock_unconditionally(&dev_data->ctx);
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return 0;
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}
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/*
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* Current factors requiring use of DT_NODELABEL:
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*
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* - NRFX_SPIS_INSTANCE() requires an SoC instance number
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* - soc-instance-numbered kconfig enables
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* - ORC is a SoC-instance-numbered kconfig option instead of a DT property
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*/
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#define SPIS(idx) DT_NODELABEL(spi##idx)
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#define SPIS_PROP(idx, prop) DT_PROP(SPIS(idx), prop)
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#define SPI_NRFX_SPIS_DEVICE(idx) \
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static int spi_##idx##_init(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_IRQN(SPIS(idx)), DT_IRQ(SPIS(idx), priority), \
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nrfx_isr, nrfx_spis_##idx##_irq_handler, 0); \
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const nrfx_spis_config_t config = { \
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.sck_pin = SPIS_PROP(idx, sck_pin), \
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.mosi_pin = SPIS_PROP(idx, mosi_pin), \
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.miso_pin = SPIS_PROP(idx, miso_pin), \
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.csn_pin = SPIS_PROP(idx, csn_pin), \
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.mode = NRF_SPIS_MODE_0, \
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.bit_order = NRF_SPIS_BIT_ORDER_MSB_FIRST, \
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.csn_pullup = NRF_GPIO_PIN_NOPULL, \
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.miso_drive = NRF_GPIO_PIN_S0S1, \
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.orc = CONFIG_SPI_##idx##_NRF_ORC, \
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.def = SPIS_PROP(idx, def_char), \
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}; \
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return init_spis(dev, &config); \
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} \
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static struct spi_nrfx_data spi_##idx##_data = { \
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SPI_CONTEXT_INIT_LOCK(spi_##idx##_data, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_##idx##_data, ctx), \
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}; \
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static const struct spi_nrfx_config spi_##idx##z_config = { \
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.spis = NRFX_SPIS_INSTANCE(idx), \
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.max_buf_len = (1 << SPIS##idx##_EASYDMA_MAXCNT_SIZE) - 1, \
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}; \
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DEVICE_AND_API_INIT(spi_##idx, \
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DT_LABEL(SPIS(idx)), \
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spi_##idx##_init, \
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&spi_##idx##_data, \
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&spi_##idx##z_config, \
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POST_KERNEL, \
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CONFIG_SPI_INIT_PRIORITY, \
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&spi_nrfx_driver_api)
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#ifdef CONFIG_SPI_0_NRF_SPIS
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SPI_NRFX_SPIS_DEVICE(0);
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#endif
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#ifdef CONFIG_SPI_1_NRF_SPIS
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SPI_NRFX_SPIS_DEVICE(1);
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#endif
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#ifdef CONFIG_SPI_2_NRF_SPIS
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SPI_NRFX_SPIS_DEVICE(2);
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#endif
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#ifdef CONFIG_SPI_3_NRF_SPIS
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SPI_NRFX_SPIS_DEVICE(3);
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#endif
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