131 lines
2.5 KiB
Plaintext
131 lines
2.5 KiB
Plaintext
/*
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* Copyright (c) 2018-2019 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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/ {
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compatible = "arm,mps2";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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led0 = &led_0;
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led1 = &led_1;
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sw0 = &user_button_0;
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sw1 = &user_button_1;
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uart-1 = &uart1;
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watchdog0 = &wdog0;
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};
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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/*
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* These SRAM and flash settings give the entire available
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* code and data memories to this secure firmware image.
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* This may conflict with mps2_an521_remote firmware. Use
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* caution when using both targets simultaneously.
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*/
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zephyr,sram = &ssram2_3;
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zephyr,flash = &ssram1;
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};
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leds {
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compatible = "gpio-leds";
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led_0: led_0 {
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gpios = <&gpio_led0 0>;
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label = "USERLED0";
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};
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led_1: led_1 {
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gpios = <&gpio_led0 1>;
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label = "USERLED1";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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user_button_0: button_0 {
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label = "USERPB0";
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gpios = <&gpio_button 0>;
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zephyr,code = <INPUT_KEY_0>;
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};
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user_button_1: button_1 {
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label = "USERPB1";
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gpios = <&gpio_button 1>;
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zephyr,code = <INPUT_KEY_1>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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/*
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* The memory regions defined below are according to AN521:
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* https://documentation-service.arm.com/static/5fa12fe9b1a7c5445f29017f
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*
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* Please see tables mentioned in individual comments below for details.
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*/
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ssram1: memory@10000000 {
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/* Table 3-2, row 6. */
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x10000000 DT_SIZE_M(4)>;
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zephyr,memory-region = "SSRAM1";
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};
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ssram2_3: memory@38000000 {
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/* Table 3-4, rows 16 and 17. */
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x38000000 DT_SIZE_M(4)>;
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zephyr,memory-region = "SSRAM2_3";
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};
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psram: memory@80000000 {
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/* Table 3-6, row 1. */
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device_type = "memory";
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reg = <0x80000000 DT_SIZE_M(16)>;
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};
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soc {
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peripheral@50000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x50000000 0x10000000>;
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#include "mps2_an521-common.dtsi"
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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&uart1 {
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status = "okay";
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};
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