337 lines
8.6 KiB
C
337 lines
8.6 KiB
C
/*
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* Copyright (c) 2023 Andes Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT andestech_atcwdt200
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/watchdog.h>
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#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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#include <zephyr/drivers/counter.h>
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#include <zephyr/drivers/syscon.h>
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LOG_MODULE_REGISTER(wdt_andes);
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/* Watchdog register */
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#define REG_IDR 0x00
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#define REG_CTRL 0x10
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#define REG_RESTAR 0x14
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#define REG_WREN 0x18
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#define REG_STATUS 0x1c
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#define WDT_CTRL(addr) (addr + REG_CTRL)
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#define WDT_RESTAR(addr) (addr + REG_RESTAR)
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#define WDT_WREN(addr) (addr + REG_WREN)
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#define WDT_STATUS(addr) (addr + REG_STATUS)
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/* Atcwdt200 magic number */
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/* 0x10 Control Register */
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#define WDT_CTRL_RSTTIME_POW_2_7 0x000
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#define WDT_CTRL_RSTTIME_POW_2_8 0x100
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#define WDT_CTRL_RSTTIME_POW_2_9 0x200
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#define WDT_CTRL_RSTTIME_POW_2_10 0x300
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#define WDT_CTRL_RSTTIME_POW_2_11 0x400
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#define WDT_CTRL_RSTTIME_POW_2_12 0x500
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#define WDT_CTRL_RSTTIME_POW_2_13 0x600
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#define WDT_CTRL_RSTTIME_POW_2_14 0x700
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#define WDT_CTRL_INTTIME_POW_2_6 0x000
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#define WDT_CTRL_INTTIME_POW_2_8 0x010
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#define WDT_CTRL_INTTIME_POW_2_10 0x020
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#define WDT_CTRL_INTTIME_POW_2_11 0x030
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#define WDT_CTRL_INTTIME_POW_2_12 0x040
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#define WDT_CTRL_INTTIME_POW_2_13 0x050
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#define WDT_CTRL_INTTIME_POW_2_14 0x060
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#define WDT_CTRL_INTTIME_POW_2_15 0x070
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#define WDT_CTRL_INTTIME_POW_2_17 0x080
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#define WDT_CTRL_INTTIME_POW_2_19 0x090
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#define WDT_CTRL_INTTIME_POW_2_21 0x0A0
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#define WDT_CTRL_INTTIME_POW_2_23 0x0B0
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#define WDT_CTRL_INTTIME_POW_2_25 0x0C0
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#define WDT_CTRL_INTTIME_POW_2_27 0x0D0
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#define WDT_CTRL_INTTIME_POW_2_29 0x0E0
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#define WDT_CTRL_INTTIME_POW_2_31 0x0F0
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#define WDT_CTRL_RSTEN 0x8
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#define WDT_CTRL_INTEN 0x4
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#define WDT_CTRL_APBCLK 0x2
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#define WDT_CTRL_EXTCLK 0x0
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#define WDT_CTRL_EN 0x1
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/* Magic Number for Restart Register */
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#define WDT_RESTART_NUM 0xcafe
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/* Magic Number for Write Enable Register */
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#define WDT_WREN_NUM 0x5aa5
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/* 0x1C Status Register */
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#define WDT_ST_INTEXPIRED 0x1
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#define WDT_ST_INTEXPIRED_CLR 0x1
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#define WDOGCFG_PERIOD_MIN BIT(7)
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#define WDOGCFG_PERIOD_MAX BIT(14)
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#define EXT_CLOCK_FREQ BIT(15)
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static const struct device *const pit_counter_dev =
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DEVICE_DT_GET(DT_NODELABEL(pit0));
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struct counter_alarm_cfg alarm_cfg;
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struct wdt_atcwdt200_config {
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uintptr_t base;
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};
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struct wdt_atcwdt200_dev_data {
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bool timeout_valid;
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counter_alarm_callback_t counter_callback;
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struct k_spinlock lock;
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};
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static int wdt_atcwdt200_disable(const struct device *dev);
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static void wdt_counter_cb(const struct device *counter_dev, uint8_t chan_id,
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uint32_t counter,
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void *user_data)
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{
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const struct device *dev = DEVICE_DT_INST_GET(0);
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struct wdt_atcwdt200_dev_data *wdt_data = dev->data;
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uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base;
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k_spinlock_key_t key;
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key = k_spin_lock(&wdt_data->lock);
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sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr));
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sys_write32(WDT_RESTART_NUM, WDT_RESTAR(wdt_addr));
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counter_set_channel_alarm(counter_dev, 2, &alarm_cfg);
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k_spin_unlock(&wdt_data->lock, key);
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}
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/**
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* @brief Set maximum length of timeout to watchdog
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*
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* @param dev Watchdog device struct
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*/
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static void wdt_atcwdt200_set_max_timeout(const struct device *dev)
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{
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struct wdt_atcwdt200_dev_data *data = dev->data;
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k_spinlock_key_t key;
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uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base;
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uint32_t reg, counter_freq;
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key = k_spin_lock(&data->lock);
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counter_freq = counter_get_frequency(pit_counter_dev);
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alarm_cfg.flags = 0;
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alarm_cfg.callback = wdt_counter_cb;
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alarm_cfg.user_data = &alarm_cfg;
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alarm_cfg.ticks = ((WDOGCFG_PERIOD_MAX * counter_freq) / EXT_CLOCK_FREQ) >> 1;
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reg = WDT_CTRL_RSTTIME_POW_2_14;
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sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr));
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sys_write32(reg, WDT_CTRL(wdt_addr));
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data->timeout_valid = true;
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k_spin_unlock(&data->lock, key);
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}
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static int wdt_atcwdt200_disable(const struct device *dev)
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{
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struct wdt_atcwdt200_dev_data *data = dev->data;
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uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base;
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k_spinlock_key_t key;
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uint32_t reg;
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key = k_spin_lock(&data->lock);
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reg = sys_read32(WDT_CTRL(wdt_addr));
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reg &= ~(WDT_CTRL_RSTEN | WDT_CTRL_EN);
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sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr));
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sys_write32(reg, WDT_CTRL(wdt_addr));
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k_spin_unlock(&data->lock, key);
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wdt_atcwdt200_set_max_timeout(dev);
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counter_cancel_channel_alarm(pit_counter_dev, 2);
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return 0;
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}
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static int wdt_atcwdt200_setup(const struct device *dev, uint8_t options)
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{
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struct wdt_atcwdt200_dev_data *data = dev->data;
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uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base;
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k_spinlock_key_t key;
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uint32_t reg;
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uint32_t ret = 0;
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if (!data->timeout_valid) {
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LOG_ERR("No valid timeouts installed");
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return -EINVAL;
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}
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key = k_spin_lock(&data->lock);
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reg = sys_read32(WDT_CTRL(wdt_addr));
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reg |= (WDT_CTRL_RSTEN | WDT_CTRL_EN);
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if ((options & WDT_OPT_PAUSE_HALTED_BY_DBG) ==
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WDT_OPT_PAUSE_HALTED_BY_DBG) {
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counter_cancel_channel_alarm(pit_counter_dev, 2);
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sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr));
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sys_write32(reg, WDT_CTRL(wdt_addr));
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goto out;
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} else {
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ret = counter_set_channel_alarm(pit_counter_dev, 2, &alarm_cfg);
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if (ret != 0) {
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ret = -EINVAL;
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goto out;
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}
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sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr));
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sys_write32(reg, WDT_CTRL(wdt_addr));
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}
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out:
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k_spin_unlock(&data->lock, key);
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return ret;
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}
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/**
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* @brief Calculates the watchdog counter value (wdogcmp0) and
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* scaler (wdogscale) to be installed in the watchdog timer
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*
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* @param timeout Timeout value in milliseconds.
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* @param scaler Pointer to return scaler power of 2
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*
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* @return Watchdog counter value
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*/
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static uint32_t wdt_atcwdt200_convtime(uint32_t timeout, uint32_t *scaler)
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{
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int i;
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uint32_t rst_period, cnt;
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cnt = (uint32_t)((timeout * EXT_CLOCK_FREQ) / 1000);
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rst_period = cnt;
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for (i = 0; i < 14 && cnt > 0; i++) {
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cnt >>= 1;
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}
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*scaler = i;
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return rst_period;
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}
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static int wdt_atcwdt200_install_timeout(const struct device *dev,
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const struct wdt_timeout_cfg *cfg)
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{
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struct wdt_atcwdt200_dev_data *data = dev->data;
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uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base;
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k_spinlock_key_t key;
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uint32_t rst_period, reg, counter_freq, scaler;
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if (cfg->window.min != 0U || cfg->window.max == 0U) {
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return -EINVAL;
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}
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counter_freq = counter_get_frequency(pit_counter_dev);
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rst_period = wdt_atcwdt200_convtime(cfg->window.max, &scaler);
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if (rst_period < 0 || WDOGCFG_PERIOD_MAX < rst_period) {
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LOG_ERR("Unsupported watchdog timeout\n");
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return -EINVAL;
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}
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wdt_atcwdt200_disable(dev);
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key = k_spin_lock(&data->lock);
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switch (cfg->flags) {
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case WDT_FLAG_RESET_SOC:
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if (scaler < 7) {
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reg = WDT_CTRL_RSTTIME_POW_2_7;
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} else {
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scaler = scaler - 7;
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reg = scaler << 8;
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}
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alarm_cfg.flags = 0;
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alarm_cfg.callback = wdt_counter_cb;
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alarm_cfg.user_data = &alarm_cfg;
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alarm_cfg.ticks = (((cfg->window.max * counter_freq) / 1000) >> 1);
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break;
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case WDT_FLAG_RESET_NONE:
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case WDT_FLAG_RESET_CPU_CORE:
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default:
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LOG_ERR("Unsupported watchdog config flags\n");
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k_spin_unlock(&data->lock, key);
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return -ENOTSUP;
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}
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sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr));
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sys_write32(reg, WDT_CTRL(wdt_addr));
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int wdt_atcwdt200_feed(const struct device *dev, int channel_id)
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{
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uint32_t wdt_addr = ((const struct wdt_atcwdt200_config *)(dev->config))->base;
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ARG_UNUSED(channel_id);
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sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr));
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sys_write32(WDT_RESTART_NUM, WDT_RESTAR(wdt_addr));
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return 0;
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}
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static const struct wdt_driver_api wdt_atcwdt200_api = {
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.setup = wdt_atcwdt200_setup,
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.disable = wdt_atcwdt200_disable,
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.install_timeout = wdt_atcwdt200_install_timeout,
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.feed = wdt_atcwdt200_feed,
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};
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static int wdt_atcwdt200_init(const struct device *dev)
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{
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struct wdt_atcwdt200_dev_data *data = dev->data;
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data->timeout_valid = false;
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data->counter_callback = wdt_counter_cb;
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counter_start(pit_counter_dev);
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#ifdef CONFIG_WDT_DISABLE_AT_BOOT
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wdt_atcwdt200_disable(dev);
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#else
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data->timeout_valid = true;
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wdt_atcwdt200_set_max_timeout(dev);
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wdt_atcwdt200_setup(dev, 0x0);
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#endif
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return 0;
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}
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static struct wdt_atcwdt200_dev_data wdt_atcwdt200_data;
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static const struct wdt_atcwdt200_config wdt_atcwdt200_cfg = {
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.base = DT_INST_REG_ADDR(0),
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};
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DEVICE_DT_INST_DEFINE(0, wdt_atcwdt200_init, NULL,
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&wdt_atcwdt200_data, &wdt_atcwdt200_cfg, PRE_KERNEL_2,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_atcwdt200_api);
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