232 lines
6.4 KiB
C
232 lines
6.4 KiB
C
/*
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* Copyright (c) 2023 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT intel_timeaware_gpio
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#include <errno.h>
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#include <stdio.h>
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#include <zephyr/device.h>
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/misc/timeaware_gpio/timeaware_gpio.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/internal/syscall_handler.h>
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/* TGPIO Register offsets */
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#define ART_L 0x00 /* ART lower 32 bit reg */
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#define ART_H 0x04 /* ART higher 32 bit reg */
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#define CTL 0x10 /* TGPIO control reg */
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#define COMPV31_0 0x20 /* Comparator lower 32 bit reg */
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#define COMPV63_32 0x24 /* Comparator higher 32 bit reg */
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#define PIV31_0 0x28 /* Periodic Interval lower 32 bit reg */
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#define PIV63_32 0x2c /* Periodic Interval higher 32 bit reg */
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#define TCV31_0 0x30 /* Time Capture lower 32 bit reg */
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#define TCV63_32 0x34 /* Time Capture higher 32 bit reg */
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#define ECCV31_0 0x38 /* Event Counter Capture lower 32 bit reg */
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#define ECCV63_32 0x3c /* Event Counter Capture higher 32 bit reg */
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#define EC31_0 0x40 /* Event Counter lower 32 bit reg */
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#define EC63_32 0x44 /* Event Counter higher 32 bit reg */
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#define REGSET_SIZE 0x100 /* Difference between 0 and 1 */
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#define UINT32_MASK 0xFFFFFFFF /* 32 bit Mask */
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#define UINT32_SIZE 32
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/* Control Register */
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#define CTL_EN BIT(0) /* Control enable */
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#define CTL_DIR BIT(1) /* Control disable */
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#define CTL_EP GENMASK(3, 2) /* Recerved polarity */
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#define CTL_EP_RISING_EDGE (0 << 2) /* Rising edge */
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#define CTL_EP_FALLING_EDGE (1 << 2) /* Falling edge */
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#define CTL_EP_TOGGLE_EDGE (2 << 2) /* Toggle edge */
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#define CTL_PM BIT(4) /* Periodic mode */
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/* Macro to get configuration data, required by DEVICE_MMIO_NAMED_* in init */
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#define DEV_CFG(_dev) \
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((const struct tgpio_config *)(_dev)->config)
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/* Macro to get runtime data, required by DEVICE_MMIO_NAMED_* in init */
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#define DEV_DATA(_dev) ((struct tgpio_runtime *)(_dev)->data)
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/* Macro to individual pin regbase */
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#define pin_regs(addr, pin) (addr + (pin * REGSET_SIZE))
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struct tgpio_config {
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DEVICE_MMIO_NAMED_ROM(reg_base);
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uint32_t max_pins;
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uint32_t art_clock_freq;
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};
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struct tgpio_runtime {
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DEVICE_MMIO_NAMED_RAM(reg_base);
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};
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static mm_reg_t regs(const struct device *dev)
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{
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return DEVICE_MMIO_NAMED_GET(dev, reg_base);
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}
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static int tgpio_intel_get_time(const struct device *dev,
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uint64_t *current_time)
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{
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*current_time = sys_read32(regs(dev) + ART_L);
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*current_time += ((uint64_t)sys_read32(regs(dev) + ART_H) << UINT32_SIZE);
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return 0;
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}
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static int tgpio_intel_cyc_per_sec(const struct device *dev,
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uint32_t *cycles)
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{
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*cycles = DEV_CFG(dev)->art_clock_freq;
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return 0;
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}
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static int tgpio_intel_pin_disable(const struct device *dev,
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uint32_t pin)
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{
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mm_reg_t addr = regs(dev);
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if (pin >= DEV_CFG(dev)->max_pins) {
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return -EINVAL;
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}
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addr = pin_regs(addr, pin);
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sys_write32(sys_read32(addr + CTL) & ~CTL_EN, addr + CTL);
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return 0;
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}
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static int tgpio_intel_periodic_output(const struct device *dev,
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uint32_t pin,
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uint64_t start_time,
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uint64_t repeat_interval,
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bool periodic_enable)
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{
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mm_reg_t addr = regs(dev);
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uint32_t val;
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if (pin >= DEV_CFG(dev)->max_pins) {
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return -EINVAL;
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}
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addr = pin_regs(addr, pin);
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tgpio_intel_pin_disable(dev, pin);
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/* Configure PIV */
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val = (repeat_interval >> UINT32_SIZE) & UINT32_MASK;
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sys_write32(val, addr + PIV63_32);
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val = repeat_interval & UINT32_MASK;
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sys_write32(val, addr + PIV31_0);
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/* Configure COMPV */
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val = (start_time >> UINT32_SIZE) & UINT32_MASK;
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sys_write32(val, addr + COMPV63_32);
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val = start_time & UINT32_MASK;
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sys_write32(val, addr + COMPV31_0);
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val = 0;
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/* Configure Periodic Mode */
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if (periodic_enable) {
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val |= CTL_PM;
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}
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/* Enable the pin */
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val |= CTL_EN;
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sys_write32(val, addr + CTL);
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return 0;
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}
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static int tgpio_intel_config_external_timestamp(const struct device *dev,
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uint32_t pin,
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uint32_t event_polarity)
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{
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mm_reg_t addr = regs(dev);
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uint32_t val;
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if (pin >= DEV_CFG(dev)->max_pins) {
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return -EINVAL;
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}
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addr = pin_regs(addr, pin);
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tgpio_intel_pin_disable(dev, pin);
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/* Configure interrupt polarity */
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if (event_polarity == 0) {
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val = CTL_EP_RISING_EDGE;
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} else if (event_polarity == 1) {
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val = CTL_EP_FALLING_EDGE;
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} else {
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val = CTL_EP_TOGGLE_EDGE;
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}
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/* Configure direction = input */
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val |= CTL_DIR;
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sys_write32(val, addr + CTL);
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/* Enable the pin */
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sys_write32(sys_read32(addr + CTL) | CTL_EN, addr + CTL);
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return 0;
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}
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static int tgpio_intel_read_ts_ec(const struct device *dev,
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uint32_t pin,
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uint64_t *timestamp,
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uint64_t *event_count)
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{
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if (pin >= DEV_CFG(dev)->max_pins) {
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return -EINVAL;
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}
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*timestamp = sys_read32(regs(dev) + TCV31_0);
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*timestamp += ((uint64_t)sys_read32(regs(dev) + TCV63_32) << UINT32_SIZE);
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*event_count = sys_read32(regs(dev) + ECCV31_0);
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*event_count += ((uint64_t)sys_read32(regs(dev) + ECCV63_32) << UINT32_SIZE);
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return 0;
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}
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static const struct tgpio_driver_api api_funcs = {
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.pin_disable = tgpio_intel_pin_disable,
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.get_time = tgpio_intel_get_time,
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.set_perout = tgpio_intel_periodic_output,
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.config_ext_ts = tgpio_intel_config_external_timestamp,
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.read_ts_ec = tgpio_intel_read_ts_ec,
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.cyc_per_sec = tgpio_intel_cyc_per_sec,
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};
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static int tgpio_init(const struct device *dev)
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{
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const struct tgpio_config *cfg = DEV_CFG(dev);
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struct tgpio_runtime *rt = DEV_DATA(dev);
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device_map(&rt->reg_base,
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cfg->reg_base.phys_addr & ~0xFFU,
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cfg->reg_base.size,
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K_MEM_CACHE_NONE);
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return 0;
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}
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#define TGPIO_INTEL_DEV_CFG_DATA(n) \
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static const struct tgpio_config \
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tgpio_##n##_cfg = { \
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DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
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.max_pins = DT_INST_PROP(n, max_pins), \
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.art_clock_freq = DT_INST_PROP(n, timer_clock), \
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}; \
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\
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static struct tgpio_runtime tgpio_##n##_runtime; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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&tgpio_init, \
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NULL, \
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&tgpio_##n##_runtime, \
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&tgpio_##n##_cfg, \
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POST_KERNEL, CONFIG_TIMEAWARE_GPIO_INIT_PRIORITY,\
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&api_funcs); \
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DT_INST_FOREACH_STATUS_OKAY(TGPIO_INTEL_DEV_CFG_DATA)
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