64 lines
1.5 KiB
Plaintext
64 lines
1.5 KiB
Plaintext
/*
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* Copyright (c) 2020 Alexander Kozhinov <AlexanderKozhinov@yandex.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/h7/stm32h7_dualcore.dtsi>
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/ {
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soc {
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flash-controller@52002000 {
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flash0: flash@8000000 {
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compatible = "soc-nv-flash";
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write-block-size = <32>;
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erase-block-size = <DT_SIZE_K(128)>;
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};
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flash1: flash@8100000 {
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compatible = "soc-nv-flash";
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write-block-size = <32>;
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erase-block-size = <DT_SIZE_K(128)>;
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};
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};
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dmamux1: dmamux@40020800 {
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dma-requests= <107>;
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};
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};
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/*
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* The RAM memories placed here can be used by both cores M4/M7
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* For more information see reference manual and datasheet to STM32H745
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* (RM0399 Rev 3)
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*/
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/* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
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sram0: memory@24000000 {
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reg = <0x24000000 DT_SIZE_K(512)>;
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compatible = "mmio-sram";
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};
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/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
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sram1: memory@30000000 {
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reg = <0x30000000 DT_SIZE_K(128)>;
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compatible = "mmio-sram";
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};
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/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
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sram2: memory@30020000 {
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compatible = "mmio-sram";
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reg = <0x30020000 DT_SIZE_K(128)>;
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};
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/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
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sram3: memory@30040000 {
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compatible = "mmio-sram";
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reg = <0x30040000 DT_SIZE_K(32)>;
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};
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/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
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sram4: memory@38000000 {
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reg = <0x38000000 DT_SIZE_K(64)>;
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compatible = "mmio-sram";
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};
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};
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