844 lines
20 KiB
Plaintext
844 lines
20 KiB
Plaintext
/*
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* Copyright (c) 2019 Linaro Limited
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* Copyright (c) 2019 Centaur Analytics, Inc
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* Copyright (c) 2020 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <dt-bindings/clock/stm32_clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/pwm/pwm.h>
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#include <dt-bindings/memory-controller/stm32-fmc-sdram.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,entropy = &rng;
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zephyr,flash-controller = &flash;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m7";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv7m-mpu";
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reg = <0xe000ed90 0x40>;
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arm,num-mpu-regions = <16>;
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};
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "st,stm32-hse-clock";
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/* H7 clock driver may not always need this value */
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/* but it is required by the binding */
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clock-frequency = <DT_FREQ_M(25)>;
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "st,stm32h7-hsi-clock";
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clock-frequency = <DT_FREQ_M(64)>;
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status = "disabled";
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};
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clk_csi: clk-csi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(4)>;
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status = "disabled";
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(32)>;
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status = "disabled";
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};
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pll: pll@0 {
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#clock-cells = <0>;
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compatible = "st,stm32h7-pll-clock";
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reg = <0>;
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status = "disabled";
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};
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pll3: pll@2 {
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#clock-cells = <0>;
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compatible = "st,stm32h7-pll-clock";
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reg = <2>;
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status = "disabled";
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};
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};
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soc {
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flash: flash-controller@52002000 {
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compatible = "st,stm32h7-flash-controller";
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label = "FLASH_CTRL";
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reg = <0x52002000 0x400>;
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interrupts = <4 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000100>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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rcc: rcc@58024400 {
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compatible = "st,stm32h7-rcc";
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#clock-cells = <2>;
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reg = <0x58024400 0x400>;
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};
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exti: interrupt-controller@58000000 {
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compatible = "st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x58000000 0x400>;
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};
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pinctrl: pin-controller@58020000 {
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compatible = "st,stm32-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x58020000 0x2400>;
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gpioa: gpio@58020000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x58020000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>;
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label = "GPIOA";
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};
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gpiob: gpio@58020400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x58020400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>;
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label = "GPIOB";
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};
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gpioc: gpio@58020800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x58020800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>;
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label = "GPIOC";
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};
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gpiod: gpio@58020C00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x58020C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>;
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label = "GPIOD";
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};
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gpioe: gpio@58021000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x58021000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>;
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label = "GPIOE";
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};
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gpiof: gpio@58021400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x58021400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>;
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label = "GPIOF";
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};
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gpiog: gpio@58021800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x58021800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000040>;
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label = "GPIOG";
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};
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gpioh: gpio@58021C00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x58021C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000080>;
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label = "GPIOH";
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};
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gpioi: gpio@58022000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x58022000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000100>;
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label = "GPIOI";
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};
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gpioj: gpio@58022400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x58022400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000200>;
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label = "GPIOJ";
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};
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gpiok: gpio@58022800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x58022800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000400>;
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label = "GPIOK";
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};
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};
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iwdg1: watchdog@58004800 {
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compatible = "st,stm32-watchdog";
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reg = <0x58004800 0x400>;
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label = "IWDG_1";
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status = "disabled";
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};
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wwdg1: watchdog@50003000 {
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compatible = "st,stm32-window-watchdog";
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reg = <0x50003000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>;
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interrupts = <0 7>;
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status = "disabled";
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label = "WWDG_1";
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};
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usart1: serial@40011000 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40011000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
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interrupts = <37 0>;
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status = "disabled";
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label = "UART_1";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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interrupts = <38 0>;
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status = "disabled";
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label = "UART_2";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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interrupts = <39 0>;
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status = "disabled";
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label = "UART_3";
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};
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uart4: serial@40004c00 {
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compatible ="st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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interrupts = <52 0>;
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status = "disabled";
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label = "UART_4";
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};
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uart5: serial@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
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interrupts = <53 0>;
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status = "disabled";
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label = "UART_5";
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};
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usart6: serial@40011400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40011400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
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interrupts = <71 0>;
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status = "disabled";
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label = "UART_6";
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};
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uart7: serial@40007800 {
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compatible = "st,stm32-uart";
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reg = <0x40007800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
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interrupts = <82 0>;
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status = "disabled";
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label = "UART_7";
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};
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uart8: serial@40007c00 {
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compatible = "st,stm32-uart";
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reg = <0x40007c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
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interrupts = <83 0>;
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status = "disabled";
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label = "UART_8";
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};
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lpuart1: serial@58000c00 {
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compatible = "st,stm32-lpuart", "st,stm32-uart";
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reg = <0x58000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000008>;
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interrupts = <142 0>;
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status = "disabled";
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label = "LPUART_1";
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};
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rtc: rtc@58004000 {
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compatible = "st,stm32-rtc";
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reg = <0x58004000 0x400>;
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interrupts = <41 0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>;
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prescaler = <32768>;
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status = "disabled";
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label = "RTC_0";
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
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interrupts = <31 0>, <32 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label = "I2C_1";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
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interrupts = <33 0>, <34 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label = "I2C_2";
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};
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i2c3: i2c@40005c00 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
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interrupts = <72 0>, <73 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label = "I2C_3";
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};
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i2c4: i2c@58001c00 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x58001c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000080>;
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interrupts = <95 0>, <96 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label = "I2C_4";
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};
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spi1: spi@40013000 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
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interrupts = <35 0>;
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status = "disabled";
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label = "SPI_1";
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};
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spi2: spi@40003800 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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interrupts = <36 0>;
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status = "disabled";
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label = "SPI_2";
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};
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spi3: spi@40003c00 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
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interrupts = <51 0>;
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status = "disabled";
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label = "SPI_3";
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};
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spi4: spi@40013400 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
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interrupts = <84 0>;
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status = "disabled";
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label = "SPI_4";
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};
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spi5: spi@40015000 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40015000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
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interrupts = <85 0>;
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status = "disabled";
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label = "SPI_5";
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};
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spi6: spi@58001400 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x58001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000020>;
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interrupts = <86 0>;
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status = "disabled";
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label = "SPI_6";
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};
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timers1: timers@40010000 {
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compatible = "st,stm32-timers";
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reg = <0x40010000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>;
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interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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status = "disabled";
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label = "TIMERS_1";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_1";
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#pwm-cells = <3>;
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};
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};
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timers2: timers@40000000 {
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
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interrupts = <28 0>;
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interrupt-names = "global";
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status = "disabled";
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label = "TIMERS_2";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <0>;
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label = "PWM_2";
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#pwm-cells = <3>;
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};
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};
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timers3: timers@40000400 {
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
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interrupts = <29 0>;
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interrupt-names = "global";
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status = "disabled";
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label = "TIMERS_3";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_3";
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#pwm-cells = <3>;
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};
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};
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timers4: timers@40000800 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40000800 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
|
|
interrupts = <30 0>;
|
|
interrupt-names = "global";
|
|
status = "disabled";
|
|
label = "TIMERS_4";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
st,prescaler = <10000>;
|
|
label = "PWM_4";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timers5: timers@40000c00 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40000c00 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
|
|
interrupts = <50 0>;
|
|
interrupt-names = "global";
|
|
status = "disabled";
|
|
label = "TIMERS_5";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
st,prescaler = <0>;
|
|
label = "PWM_5";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timers6: timers@40001000 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40001000 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
|
|
interrupts = <54 0>;
|
|
interrupt-names = "global";
|
|
status = "disabled";
|
|
label = "TIMERS_6";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
st,prescaler = <10000>;
|
|
label = "PWM_6";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timers7: timers@40001400 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40001400 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
|
|
interrupts = <55 0>;
|
|
interrupt-names = "global";
|
|
status = "disabled";
|
|
label = "TIMERS_7";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
st,prescaler = <10000>;
|
|
label = "PWM_7";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timers8: timers@40010400 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40010400 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
|
|
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
|
|
interrupt-names = "brk", "up", "trgcom", "cc";
|
|
status = "disabled";
|
|
label = "TIMERS_8";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
st,prescaler = <10000>;
|
|
label = "PWM_8";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timers12: timers@40001800 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40001800 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
|
|
interrupts = <43 0>;
|
|
interrupt-names = "global";
|
|
status = "disabled";
|
|
label = "TIMERS_12";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
st,prescaler = <10000>;
|
|
label = "PWM_12";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timers13: timers@40001c00 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40001c00 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
|
|
interrupts = <44 0>;
|
|
interrupt-names = "global";
|
|
status = "disabled";
|
|
label = "TIMERS_13";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
st,prescaler = <10000>;
|
|
label = "PWM_13";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timers14: timers@40002000 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40002000 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
|
|
interrupts = <45 0>;
|
|
interrupt-names = "global";
|
|
status = "disabled";
|
|
label = "TIMERS_14";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
st,prescaler = <10000>;
|
|
label = "PWM_14";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timers15: timers@40014000 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014000 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
|
|
interrupts = <116 0>;
|
|
interrupt-names = "global";
|
|
status = "disabled";
|
|
label = "TIMERS_15";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
st,prescaler = <10000>;
|
|
label = "PWM_15";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timers16: timers@40014400 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014400 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
|
|
interrupts = <117 0>;
|
|
interrupt-names = "global";
|
|
status = "disabled";
|
|
label = "TIMERS_16";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
st,prescaler = <10000>;
|
|
label = "PWM_16";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timers17: timers@40014800 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014800 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
|
|
interrupts = <118 0>;
|
|
interrupt-names = "global";
|
|
status = "disabled";
|
|
label = "TIMERS_17";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
st,prescaler = <10000>;
|
|
label = "PWM_17";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
adc1: adc@40022000 {
|
|
compatible = "st,stm32-adc";
|
|
reg = <0x40022000 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
|
|
interrupts = <18 0>;
|
|
status = "disabled";
|
|
label = "ADC_1";
|
|
#io-channel-cells = <1>;
|
|
};
|
|
|
|
adc2: adc@40022100 {
|
|
compatible = "st,stm32-adc";
|
|
reg = <0x40022100 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
|
|
interrupts = <18 0>;
|
|
status = "disabled";
|
|
label = "ADC_2";
|
|
#io-channel-cells = <1>;
|
|
};
|
|
|
|
/* dual mode: adc1 and adc2 coupled */
|
|
adc1_2: adc@40022300 {
|
|
compatible = "st,stm32-adc";
|
|
reg = <0x40022300 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
|
|
interrupts = <18 0>;
|
|
status = "disabled";
|
|
label = "ADC_1_2";
|
|
#io-channel-cells = <1>;
|
|
};
|
|
|
|
adc3: adc@58026000 {
|
|
compatible = "st,stm32-adc";
|
|
reg = <0x58026000 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x01000000>;
|
|
interrupts = <127 0>;
|
|
status = "disabled";
|
|
label = "ADC_3";
|
|
#io-channel-cells = <1>;
|
|
};
|
|
|
|
dac1: dac@40007400 {
|
|
compatible = "st,stm32-dac";
|
|
reg = <0x40007400 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
|
|
status = "disabled";
|
|
label = "DAC_1";
|
|
#io-channel-cells = <1>;
|
|
};
|
|
|
|
dma1: dma@40020000 {
|
|
compatible = "st,stm32-dma-v1";
|
|
#dma-cells = <4>;
|
|
reg = <0x40020000 0x400>;
|
|
interrupts = <11 0>, <12 0>, <13 0>, <14 0>, <15 0>, <16 0>,
|
|
<17 0>, <47 0>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
|
|
st,mem2mem;
|
|
dma-offset = <0>;
|
|
dma-requests = <8>;
|
|
status = "disabled";
|
|
label = "DMA_1";
|
|
};
|
|
|
|
dma2: dma@40020400 {
|
|
compatible = "st,stm32-dma-v1";
|
|
#dma-cells = <4>;
|
|
reg = <0x40020400 0x400>;
|
|
interrupts = <56 0>, <57 0>, <58 0>, <59 0>, <60 0>, <68 0>,
|
|
<69 0>, <70 0>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
|
|
st,mem2mem;
|
|
dma-offset = <8>;
|
|
dma-requests = <8>;
|
|
status = "disabled";
|
|
label = "DMA_2";
|
|
};
|
|
|
|
dmamux1: dmamux@40020800 {
|
|
compatible = "st,stm32-dmamux";
|
|
#dma-cells = <4>;
|
|
reg = <0x40020800 0x400>;
|
|
interrupts = <102 0>;
|
|
/* dmamux1 has no dedicated clock, so we enable dma1 clock */
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
|
|
dma-channels = <16>;
|
|
dma-generators = <8>;
|
|
status = "disabled";
|
|
label = "DMAMUX_1";
|
|
/*
|
|
* dma-requests is different among h7 socs,
|
|
* so we set in specific dtsi files
|
|
*/
|
|
};
|
|
|
|
rng: rng@48021800 {
|
|
compatible = "st,stm32-rng";
|
|
reg = <0x48021800 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
|
|
interrupts = <80 0>;
|
|
status = "disabled";
|
|
label = "RNG";
|
|
};
|
|
|
|
mac: ethernet@40028000 {
|
|
compatible = "st,stm32-ethernet";
|
|
reg = <0x40028000 0x8000>;
|
|
label = "ETH_0";
|
|
interrupts = <61 0>;
|
|
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00008000>,
|
|
<&rcc STM32_CLOCK_BUS_AHB1 0x00010000>,
|
|
<&rcc STM32_CLOCK_BUS_AHB1 0x00020000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
fmc: memory-controller@52004000 {
|
|
compatible = "st,stm32-fmc";
|
|
reg = <0x52004000 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00001000>;
|
|
label = "STM32_FMC";
|
|
status = "disabled";
|
|
|
|
sdram: sdram {
|
|
compatible = "st,stm32-fmc-sdram";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
label = "STM32_FMC_SDRAM";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
backup_sram: memory@38800000 {
|
|
compatible = "st,stm32-backup-sram";
|
|
reg = <0x38800000 DT_SIZE_K(4)>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x10000000>;
|
|
label = "BACKUP_SRAM";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
&nvic {
|
|
arm,num-irq-priority-bits = <4>;
|
|
};
|