74 lines
1.5 KiB
Plaintext
74 lines
1.5 KiB
Plaintext
/*
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* Copyright (c) 2017 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/f4/stm32f401.dtsi>
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/ {
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soc {
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spi4: spi@40013400 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013400 0x400>;
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interrupts = <84 5>;
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status = "disabled";
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label = "SPI_4";
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};
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spi5: spi@40015000 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40015000 0x400>;
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interrupts = <85 5>;
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status = "disabled";
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label = "SPI_5";
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};
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i2s1: i2s@40013000 {
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compatible = "st,stm32-i2s";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
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interrupts = <35 5>;
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dmas = <&dma2 3 3 0x400 0x3
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&dma2 2 3 0x400 0x3>;
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dma-names = "tx", "rx";
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status = "disabled";
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label = "I2S_1";
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};
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i2s4: i2s@40013400 {
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compatible = "st,stm32-i2s";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
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interrupts = <84 5>;
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dmas = <&dma2 1 4 0x400 0x3
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&dma2 0 4 0x400 0x3>;
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dma-names = "tx", "rx";
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status = "disabled";
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label = "I2S_4";
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};
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i2s5: i2s@40015000 {
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compatible = "st,stm32-i2s";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40015000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
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interrupts = <85 5>;
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dmas = <&dma2 6 7 0x400 0x3
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&dma2 5 7 0x400 0x3>;
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dma-names = "tx", "rx";
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status = "disabled";
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label = "I2S_5";
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};
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};
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};
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