zephyr/dts/arm/st/f4/stm32f411.dtsi

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/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f401.dtsi>
/ {
soc {
spi4: spi@40013400 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013400 0x400>;
interrupts = <84 5>;
status = "disabled";
label = "SPI_4";
};
spi5: spi@40015000 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015000 0x400>;
interrupts = <85 5>;
status = "disabled";
label = "SPI_5";
};
i2s1: i2s@40013000 {
compatible = "st,stm32-i2s";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
interrupts = <35 5>;
dmas = <&dma2 3 3 0x400 0x3
&dma2 2 3 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_1";
};
i2s4: i2s@40013400 {
compatible = "st,stm32-i2s";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
interrupts = <84 5>;
dmas = <&dma2 1 4 0x400 0x3
&dma2 0 4 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_4";
};
i2s5: i2s@40015000 {
compatible = "st,stm32-i2s";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
interrupts = <85 5>;
dmas = <&dma2 6 7 0x400 0x3
&dma2 5 7 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_5";
};
};
};