410 lines
8.9 KiB
Plaintext
410 lines
8.9 KiB
Plaintext
/*
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* Copyright (c) 2017 I-SENSE group of ICCS
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* Copyright (c) 2019 Centaur Analytics, Inc
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <dt-bindings/clock/stm32_clock.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pwm/pwm.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,flash-controller = &flash;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "st,stm32-hse-clock";
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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status = "disabled";
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(40)>;
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status = "disabled";
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};
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pll: pll {
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#clock-cells = <0>;
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compatible = "st,stm32f0-pll-clock";
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status = "disabled";
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};
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};
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soc {
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flash: flash-controller@40022000 {
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compatible = "st,stm32-flash-controller", "st,stm32f3-flash-controller";
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label = "FLASH_CTRL";
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reg = <0x40022000 0x400>;
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interrupts = <4 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "soc-nv-flash";
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label = "FLASH_STM32";
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write-block-size = <2>;
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erase-block-size = <2048>;
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};
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};
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rcc: rcc@40021000 {
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compatible = "st,stm32-rcc";
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#clock-cells = <2>;
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reg = <0x40021000 0x400>;
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};
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exti: interrupt-controller@40010400 {
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compatible = "st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x40010400 0x400>;
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};
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pinctrl: pin-controller@48000000 {
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compatible = "st,stm32-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x48000000 0x1800>;
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gpioa: gpio@48000000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00020000>;
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label = "GPIOA";
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};
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gpiob: gpio@48000400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
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label = "GPIOB";
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};
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gpioc: gpio@48000800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00080000>;
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label = "GPIOC";
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};
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gpiod: gpio@48000c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00100000>;
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label = "GPIOD";
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};
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gpiof: gpio@48001400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00400000>;
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label = "GPIOF";
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};
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};
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iwdg: watchdog@40003000 {
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compatible = "st,stm32-watchdog";
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reg = <0x40003000 0x400>;
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label = "IWDG";
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status = "disabled";
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};
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wwdg: watchdog@40002c00 {
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compatible = "st,stm32-window-watchdog";
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reg = <0x40002C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
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label = "WWDG";
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interrupts = <0 7>;
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status = "disabled";
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};
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
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interrupts = <37 0>;
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status = "disabled";
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label = "UART_1";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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interrupts = <38 0>;
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status = "disabled";
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label = "UART_2";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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interrupts = <39 0>;
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status = "disabled";
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label = "UART_3";
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
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interrupts = <31 0>, <32 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_1";
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};
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spi1: spi@40013000 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
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interrupts = <35 5>;
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status = "disabled";
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label = "SPI_1";
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};
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usb: usb@40005c00 {
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compatible = "st,stm32-usb";
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reg = <0x40005c00 0x400>;
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interrupts = <20 0>;
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interrupt-names = "usb";
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num-bidir-endpoints = <8>;
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ram-size = <512>;
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phys = <&usb_fs_phy>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
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status = "disabled";
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label= "USB";
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};
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timers2: timers@40000000 {
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
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interrupts = <28 0>;
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interrupt-names = "global";
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status = "disabled";
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label = "TIMERS_2";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <0>;
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label = "PWM_2";
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#pwm-cells = <3>;
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};
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};
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timers3: timers@40000400 {
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
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interrupts = <29 0>;
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interrupt-names = "global";
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status = "disabled";
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label = "TIMERS_3";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_3";
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#pwm-cells = <3>;
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};
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};
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timers6: timers@40001000 {
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compatible = "st,stm32-timers";
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reg = <0x40001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
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interrupts = <54 0>;
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interrupt-names = "global";
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status = "disabled";
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label = "TIMERS_6";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_6";
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#pwm-cells = <3>;
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};
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};
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timers7: timers@40001400 {
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compatible = "st,stm32-timers";
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reg = <0x40001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
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interrupts = <55 0>;
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interrupt-names = "global";
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status = "disabled";
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label = "TIMERS_7";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_7";
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#pwm-cells = <3>;
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};
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};
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timers15: timers@40014000 {
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compatible = "st,stm32-timers";
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reg = <0x40014000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
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interrupts = <24 0>;
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interrupt-names = "global";
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status = "disabled";
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label = "TIMERS_15";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_15";
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#pwm-cells = <3>;
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};
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};
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timers16: timers@40014400 {
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compatible = "st,stm32-timers";
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reg = <0x40014400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
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interrupts = <25 0>;
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interrupt-names = "global";
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status = "disabled";
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label = "TIMERS_16";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_16";
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#pwm-cells = <3>;
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};
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};
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timers17: timers@40014800 {
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compatible = "st,stm32-timers";
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reg = <0x40014800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
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interrupts = <26 0>;
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interrupt-names = "global";
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status = "disabled";
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label = "TIMERS_17";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_17";
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#pwm-cells = <3>;
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};
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};
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rtc: rtc@40002800 {
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compatible = "st,stm32-rtc";
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reg = <0x40002800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
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interrupts = <41 0>;
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prescaler = <32768>;
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status = "disabled";
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label = "RTC_0";
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};
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can1: can@40006400 {
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compatible = "st,stm32-can";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40006400 0x400>;
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interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
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interrupt-names = "TX", "RX0", "RX1", "SCE";
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
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status = "disabled";
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label = "CAN_1";
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bus-speed = <125000>;
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sjw = <1>;
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prop-seg = <0>;
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phase-seg1 = <5>;
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phase-seg2 = <6>;
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};
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dma1: dma@40020000 {
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compatible = "st,stm32-dma-v2";
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#dma-cells = <4>;
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reg = <0x40020000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
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interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
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status = "disabled";
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label = "DMA_1";
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};
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};
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usb_fs_phy: usbphy {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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label = "USB_FS_PHY";
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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