38 lines
1.2 KiB
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38 lines
1.2 KiB
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Zephyr support status on RISC-V processors
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##########################################
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Overview
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********
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This page describes current state of Zephyr for RISC-V processors.
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Currently, there's support for some boards, as well as Qemu support
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and support for some FPGA implementations such as neorv32 and
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litex_vexriscv.
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Zephyr support includes PMP, :ref:`user mode<usermode_api>`, several
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ISA extensions as well as :ref:`semihosting<semihost_guide>`.
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User mode and PMP support
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**************************
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When the platform has Physical Memory Protection (PMP) support, enabling
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it on Zephyr allows user space support and stack protection to be
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selected.
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ISA extensions
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**************
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It's possible to set in Zephyr which ISA extensions (RV32/64I(E)MAFD(G)QC)
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are available on a given platform, by setting the appropriate ``CONFIG_RISCV_ISA_*``
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kconfig. Look at :file:`arch/riscv/Kconfig.isa` for more information.
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Note that Zephyr SDK toolchain support may not be defined for all
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combinations.
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SMP support
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***********
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SMP is supported on RISC-V, but currently only on Qemu platforms. In
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order to test the SMP support, one can use ``qemu_riscv32_smp`` or
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``qemu_riscv64_smp`` boards.
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