67 lines
981 B
Plaintext
67 lines
981 B
Plaintext
# Copyright (c) 2023-2024 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_UP_SQUARED_PRO_7000
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config BUILD_OUTPUT_STRIPPED
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default y
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config MP_MAX_NUM_CPUS
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default 2
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# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 1900000000 if APIC_TSC_DEADLINE_TIMER
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default 1900000000 if APIC_TIMER_TSC
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default 19200000
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if APIC_TIMER
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config APIC_TIMER_IRQ
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default 24
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endif
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if APIC_TIMER_TSC
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config APIC_TIMER_TSC_M
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default 3
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config APIC_TIMER_TSC_N
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default 249
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endif
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config ACPI
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default y
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if ACPI
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config HEAP_MEM_POOL_ADD_SIZE_ACPI
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default 64000000
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config MAIN_STACK_SIZE
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default 320000
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if SHELL
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config SHELL_STACK_SIZE
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default 320000
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endif # SHELL
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endif # ACPI
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if DMA
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config DMA_64BIT
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default y
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config DMA_DW_HW_LLI
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default n
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config DMA_DW_CHANNEL_COUNT
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default 2
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endif
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config UART_NS16550_INTEL_LPSS_DMA
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default y
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config HAS_COVERAGE_SUPPORT
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default y
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endif # BOARD_UP_SQUARED_PRO_7000
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