440 lines
11 KiB
C
440 lines
11 KiB
C
/*
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* Copyright (c) 2024 espros photonics Co.
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* Copyright (c) 2024 Espressif Systems (Shanghai) CO LTD.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT espressif_esp32_lcd_cam
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#include <soc/gdma_channel.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/esp32_clock_control.h>
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#include <zephyr/drivers/dma.h>
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#include <zephyr/drivers/dma/dma_esp32.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/video.h>
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#include <zephyr/kernel.h>
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#include <hal/cam_hal.h>
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#include <hal/cam_ll.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(video_esp32_lcd_cam, CONFIG_VIDEO_LOG_LEVEL);
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#define VIDEO_ESP32_DMA_BUFFER_MAX_SIZE 4095
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enum video_esp32_cam_clk_sel_values {
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VIDEO_ESP32_CAM_CLK_SEL_NONE = 0,
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VIDEO_ESP32_CAM_CLK_SEL_XTAL = 1,
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VIDEO_ESP32_CAM_CLK_SEL_PLL_DIV2 = 2,
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VIDEO_ESP32_CAM_CLK_SEL_PLL_F160M = 3,
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};
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struct video_esp32_config {
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const struct pinctrl_dev_config *pcfg;
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const struct device *clock_dev;
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const clock_control_subsys_t clock_subsys;
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const struct device *dma_dev;
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const struct device *source_dev;
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uint32_t cam_clk;
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uint8_t rx_dma_channel;
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uint8_t data_width;
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uint8_t invert_de;
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uint8_t invert_byte_order;
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uint8_t invert_bit_order;
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uint8_t invert_pclk;
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uint8_t invert_hsync;
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uint8_t invert_vsync;
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};
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struct video_esp32_data {
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cam_hal_context_t hal;
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const struct video_esp32_config *config;
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struct video_format video_format;
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struct video_buffer *active_vbuf;
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bool is_streaming;
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struct k_fifo fifo_in;
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struct k_fifo fifo_out;
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struct dma_block_config dma_blocks[CONFIG_DMA_ESP32_MAX_DESCRIPTOR_NUM];
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};
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static int video_esp32_reload_dma(struct video_esp32_data *data)
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{
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const struct video_esp32_config *cfg = data->config;
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int ret = 0;
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if (data->active_vbuf == NULL) {
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LOG_ERR("No video buffer available. Enqueue some buffers first.");
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return -EAGAIN;
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}
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ret = dma_reload(cfg->dma_dev, cfg->rx_dma_channel, 0, (uint32_t)data->active_vbuf->buffer,
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data->active_vbuf->bytesused);
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if (ret) {
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LOG_ERR("Unable to reload DMA (%d)", ret);
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return ret;
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}
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ret = dma_start(cfg->dma_dev, cfg->rx_dma_channel);
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if (ret) {
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LOG_ERR("Unable to start DMA (%d)", ret);
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return ret;
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}
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return 0;
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}
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void video_esp32_dma_rx_done(const struct device *dev, void *user_data, uint32_t channel,
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int status)
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{
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struct video_esp32_data *data = user_data;
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int ret = 0;
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if (status == DMA_STATUS_BLOCK) {
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LOG_DBG("received block");
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return;
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}
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if (status != DMA_STATUS_COMPLETE) {
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LOG_ERR("DMA error: %d", status);
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return;
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}
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if (data->active_vbuf == NULL) {
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LOG_ERR("No video buffer available. Enque some buffers first.");
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return;
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}
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k_fifo_put(&data->fifo_out, data->active_vbuf);
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data->active_vbuf = k_fifo_get(&data->fifo_in, K_NO_WAIT);
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if (data->active_vbuf == NULL) {
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LOG_WRN("Frame dropped. No buffer available");
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return;
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}
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video_esp32_reload_dma(data);
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}
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static int video_esp32_stream_start(const struct device *dev)
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{
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const struct video_esp32_config *cfg = dev->config;
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struct video_esp32_data *data = dev->data;
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struct dma_status dma_status = {0};
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struct dma_config dma_cfg = {0};
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struct dma_block_config *dma_block_iter = data->dma_blocks;
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uint32_t buffer_size = 0;
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int error = 0;
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if (data->is_streaming) {
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return -EBUSY;
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}
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LOG_DBG("Start streaming");
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error = dma_get_status(cfg->dma_dev, cfg->rx_dma_channel, &dma_status);
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if (error) {
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LOG_ERR("Unable to get Rx status (%d)", error);
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return error;
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}
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if (dma_status.busy) {
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LOG_ERR("Rx DMA Channel %d is busy", cfg->rx_dma_channel);
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return -EBUSY;
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}
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data->active_vbuf = k_fifo_get(&data->fifo_in, K_NO_WAIT);
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if (!data->active_vbuf) {
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LOG_ERR("No enqueued video buffers available.");
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return -EAGAIN;
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}
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buffer_size = data->active_vbuf->bytesused;
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memset(data->dma_blocks, 0, sizeof(data->dma_blocks));
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for (int i = 0; i < CONFIG_DMA_ESP32_MAX_DESCRIPTOR_NUM; ++i) {
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dma_block_iter->dest_address =
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(uint32_t)data->active_vbuf->buffer + (i * VIDEO_ESP32_DMA_BUFFER_MAX_SIZE);
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if (buffer_size < VIDEO_ESP32_DMA_BUFFER_MAX_SIZE) {
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dma_block_iter->block_size = buffer_size;
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dma_block_iter->next_block = NULL;
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dma_cfg.block_count = i + 1;
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break;
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}
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dma_block_iter->block_size = VIDEO_ESP32_DMA_BUFFER_MAX_SIZE;
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dma_block_iter->next_block = dma_block_iter + 1;
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dma_block_iter++;
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buffer_size -= VIDEO_ESP32_DMA_BUFFER_MAX_SIZE;
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}
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if (dma_block_iter->next_block) {
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LOG_ERR("Not enough descriptors available. Increase "
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"CONFIG_DMA_ESP32_MAX_DESCRIPTOR_NUM");
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return -ENOBUFS;
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}
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dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
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dma_cfg.dma_callback = video_esp32_dma_rx_done;
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dma_cfg.user_data = data;
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dma_cfg.dma_slot = SOC_GDMA_TRIG_PERIPH_CAM0;
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dma_cfg.complete_callback_en = 1;
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dma_cfg.head_block = &data->dma_blocks[0];
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error = dma_config(cfg->dma_dev, cfg->rx_dma_channel, &dma_cfg);
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if (error) {
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LOG_ERR("Unable to configure DMA (%d)", error);
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return error;
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}
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error = dma_start(cfg->dma_dev, cfg->rx_dma_channel);
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if (error) {
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LOG_ERR("Unable to start DMA (%d)", error);
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return error;
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}
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cam_hal_start_streaming(&data->hal);
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if (video_stream_start(cfg->source_dev)) {
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return -EIO;
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}
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data->is_streaming = true;
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return 0;
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}
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static int video_esp32_stream_stop(const struct device *dev)
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{
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const struct video_esp32_config *cfg = dev->config;
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struct video_esp32_data *data = dev->data;
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int ret = 0;
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LOG_DBG("Stop streaming");
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if (video_stream_stop(cfg->source_dev)) {
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return -EIO;
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}
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data->is_streaming = false;
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ret = dma_stop(cfg->dma_dev, cfg->rx_dma_channel);
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if (ret) {
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LOG_ERR("Unable to stop DMA (%d)", ret);
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return ret;
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}
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cam_hal_stop_streaming(&data->hal);
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return 0;
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}
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static int video_esp32_get_caps(const struct device *dev, enum video_endpoint_id ep,
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struct video_caps *caps)
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{
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const struct video_esp32_config *config = dev->config;
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if (ep != VIDEO_EP_OUT) {
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return -EINVAL;
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}
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/* Forward the message to the source device */
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return video_get_caps(config->source_dev, ep, caps);
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}
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static int video_esp32_get_fmt(const struct device *dev, enum video_endpoint_id ep,
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struct video_format *fmt)
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{
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const struct video_esp32_config *cfg = dev->config;
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int ret = 0;
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LOG_DBG("Get format");
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if (fmt == NULL || ep != VIDEO_EP_OUT) {
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return -EINVAL;
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}
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ret = video_get_format(cfg->source_dev, ep, fmt);
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if (ret) {
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LOG_ERR("Failed to get format from source");
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return ret;
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}
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return 0;
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}
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static int video_esp32_set_fmt(const struct device *dev, enum video_endpoint_id ep,
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struct video_format *fmt)
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{
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const struct video_esp32_config *cfg = dev->config;
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struct video_esp32_data *data = dev->data;
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if (fmt == NULL || ep != VIDEO_EP_OUT) {
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return -EINVAL;
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}
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data->video_format = *fmt;
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return video_set_format(cfg->source_dev, ep, fmt);
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}
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static int video_esp32_enqueue(const struct device *dev, enum video_endpoint_id ep,
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struct video_buffer *vbuf)
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{
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const struct video_esp32_config *cfg = dev->config;
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struct video_esp32_data *data = dev->data;
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if (ep != VIDEO_EP_OUT) {
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return -EINVAL;
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}
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vbuf->bytesused = data->video_format.pitch * data->video_format.height;
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k_fifo_put(&data->fifo_in, vbuf);
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return 0;
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}
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static int video_esp32_dequeue(const struct device *dev, enum video_endpoint_id ep,
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struct video_buffer **vbuf, k_timeout_t timeout)
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{
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struct video_esp32_data *data = dev->data;
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if (ep != VIDEO_EP_OUT) {
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return -EINVAL;
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}
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*vbuf = k_fifo_get(&data->fifo_out, timeout);
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LOG_DBG("Dequeue done, vbuf = %p", *vbuf);
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if (*vbuf == NULL) {
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return -EAGAIN;
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}
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return 0;
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}
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static int video_esp32_set_ctrl(const struct device *dev, unsigned int cid, void *value)
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{
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const struct video_esp32_config *cfg = dev->config;
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return video_set_ctrl(cfg->source_dev, cid, value);
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}
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static int video_esp32_get_ctrl(const struct device *dev, unsigned int cid, void *value)
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{
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const struct video_esp32_config *cfg = dev->config;
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return video_get_ctrl(cfg->source_dev, cid, value);
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}
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static void video_esp32_cam_ctrl_init(const struct device *dev)
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{
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const struct video_esp32_config *cfg = dev->config;
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struct video_esp32_data *data = dev->data;
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const cam_hal_config_t hal_cfg = {
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.port = 0,
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.byte_swap_en = cfg->invert_byte_order,
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};
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cam_hal_init(&data->hal, &hal_cfg);
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cam_ll_reverse_dma_data_bit_order(data->hal.hw, cfg->invert_bit_order);
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cam_ll_enable_invert_pclk(data->hal.hw, cfg->invert_pclk);
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cam_ll_set_input_data_width(data->hal.hw, cfg->data_width);
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cam_ll_enable_invert_de(data->hal.hw, cfg->invert_de);
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cam_ll_enable_invert_vsync(data->hal.hw, cfg->invert_vsync);
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cam_ll_enable_invert_hsync(data->hal.hw, cfg->invert_hsync);
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}
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static int video_esp32_init(const struct device *dev)
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{
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const struct video_esp32_config *cfg = dev->config;
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struct video_esp32_data *data = dev->data;
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k_fifo_init(&data->fifo_in);
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k_fifo_init(&data->fifo_out);
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data->config = cfg;
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video_esp32_cam_ctrl_init(dev);
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if (!device_is_ready(cfg->dma_dev)) {
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LOG_ERR("DMA device not ready");
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return -ENODEV;
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}
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return 0;
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}
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static const struct video_driver_api esp32_driver_api = {
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/* mandatory callbacks */
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.set_format = video_esp32_set_fmt,
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.get_format = video_esp32_get_fmt,
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.stream_start = video_esp32_stream_start,
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.stream_stop = video_esp32_stream_stop,
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.get_caps = video_esp32_get_caps,
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/* optional callbacks */
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.enqueue = video_esp32_enqueue,
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.dequeue = video_esp32_dequeue,
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.flush = NULL,
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.set_ctrl = video_esp32_set_ctrl,
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.get_ctrl = video_esp32_get_ctrl,
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.set_signal = NULL,
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};
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PINCTRL_DT_INST_DEFINE(0);
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static const struct video_esp32_config esp32_config = {
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
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.source_dev = DEVICE_DT_GET(DT_INST_PHANDLE(0, source)),
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.dma_dev = ESP32_DT_INST_DMA_CTLR(0, rx),
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.rx_dma_channel = DT_INST_DMAS_CELL_BY_NAME(0, rx, channel),
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.data_width = DT_INST_PROP_OR(0, data_width, 8),
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.invert_bit_order = DT_INST_PROP(0, invert_bit_order),
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.invert_byte_order = DT_INST_PROP(0, invert_byte_order),
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.invert_pclk = DT_INST_PROP(0, invert_pclk),
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.invert_de = DT_INST_PROP(0, invert_de),
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.invert_hsync = DT_INST_PROP(0, invert_hsync),
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.invert_vsync = DT_INST_PROP(0, invert_vsync),
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.cam_clk = DT_INST_PROP_OR(0, cam_clk, 0),
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
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.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(0, offset),
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};
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static struct video_esp32_data esp32_data = {0};
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DEVICE_DT_INST_DEFINE(0, video_esp32_init, NULL, &esp32_data, &esp32_config,
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POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY, &esp32_driver_api);
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static int video_esp32_cam_init_master_clock(void)
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{
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int ret = 0;
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ret = pinctrl_apply_state(esp32_config.pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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printk("video pinctrl setup failed (%d)", ret);
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return ret;
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}
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/* Enable peripheral */
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if (!device_is_ready(esp32_config.clock_dev)) {
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return -ENODEV;
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}
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clock_control_on(esp32_config.clock_dev, esp32_config.clock_subsys);
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if (!esp32_config.cam_clk) {
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printk("No cam_clk specified\n");
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return -EINVAL;
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}
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if (ESP32_CLK_CPU_PLL_160M % esp32_config.cam_clk) {
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printk("Invalid cam_clk value. It must be a divisor of 160M\n");
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return -EINVAL;
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}
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/* Enable camera master clock output */
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cam_ll_select_clk_src(0, LCD_CLK_SRC_PLL160M);
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cam_ll_set_group_clock_coeff(0, ESP32_CLK_CPU_PLL_160M / esp32_config.cam_clk, 0, 0);
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return 0;
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}
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SYS_INIT(video_esp32_cam_init_master_clock, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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