433 lines
14 KiB
C
433 lines
14 KiB
C
/*
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* Copyright (c) 2022 ITE Corporation. All Rights Reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ite_it8xxx2_pinctrl_func
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/logging/log.h>
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#include <chip_chipregs.h>
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LOG_MODULE_REGISTER(pinctrl_ite_it8xxx2, LOG_LEVEL_ERR);
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#define GPIO_IT8XXX2_REG_BASE \
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((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr)))
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#define GPIO_GROUP_MEMBERS 8
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struct pinctrl_it8xxx2_gpio {
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/* gpio port control register (byte mapping to pin) */
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uint8_t *reg_gpcr;
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/* port driving select control */
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uint8_t *reg_pdsc;
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/* function 3 general control register */
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uintptr_t func3_gcr[GPIO_GROUP_MEMBERS];
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/* function 3 enable mask */
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uint8_t func3_en_mask[GPIO_GROUP_MEMBERS];
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/* function 3 external control register */
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uintptr_t func3_ext[GPIO_GROUP_MEMBERS];
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/* function 3 external mask */
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uint8_t func3_ext_mask[GPIO_GROUP_MEMBERS];
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/* function 4 general control register */
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uintptr_t func4_gcr[GPIO_GROUP_MEMBERS];
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/* function 4 enable mask */
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uint8_t func4_en_mask[GPIO_GROUP_MEMBERS];
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/* Input voltage selection */
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uintptr_t volt_sel[GPIO_GROUP_MEMBERS];
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/* Input voltage selection mask */
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uint8_t volt_sel_mask[GPIO_GROUP_MEMBERS];
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};
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struct pinctrl_it8xxx2_ksi_kso {
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/*
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* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register
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* (bit mapping to pin)
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*/
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uint8_t *reg_gctrl;
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/* KSI[7:0]/KSO[15:8]/KSO[7:0] port control register */
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uint8_t *reg_ctrl;
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/*
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* KSO push-pull/open-drain bit of KSO[15:0] control register
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* (this bit apply to all pins)
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*/
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int pp_od_mask;
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/*
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* KSI/KSO pullup bit of KSI[7:0]/KSO[15:0] control register
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* (this bit apply to all pins)
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*/
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int pullup_mask;
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};
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struct pinctrl_it8xxx2_config {
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bool gpio_group;
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union {
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struct pinctrl_it8xxx2_gpio gpio;
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struct pinctrl_it8xxx2_ksi_kso ksi_kso;
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};
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};
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static int pinctrl_it8xxx2_set(const pinctrl_soc_pin_t *pins)
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{
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const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
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const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio);
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uint32_t pincfg = pins->pincfg;
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uint8_t pin = pins->pin;
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volatile uint8_t *reg_gpcr = (uint8_t *)gpio->reg_gpcr + pin;
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volatile uint8_t *reg_volt_sel = (uint8_t *)(gpio->volt_sel[pin]);
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volatile uint8_t *reg_pdsc = (uint8_t *)gpio->reg_pdsc;
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/* Setting pull-up or pull-down. */
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switch (IT8XXX2_DT_PINCFG_PUPDR(pincfg)) {
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case IT8XXX2_PULL_PIN_DEFAULT:
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/* No pull-up or pull-down */
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*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_PULLUP |
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GPCR_PORT_PIN_MODE_PULLDOWN);
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break;
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case IT8XXX2_PULL_UP:
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLUP) &
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~GPCR_PORT_PIN_MODE_PULLDOWN;
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break;
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case IT8XXX2_PULL_DOWN:
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLDOWN) &
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~GPCR_PORT_PIN_MODE_PULLUP;
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break;
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default:
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LOG_ERR("This pull level is not supported.");
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return -EINVAL;
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}
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/*
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* Since not all GPIOs support voltage selection, configure voltage
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* selection register only if it is present.
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*/
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if (reg_volt_sel != NULL) {
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/* Setting voltage 3.3V or 1.8V. */
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switch (IT8XXX2_DT_PINCFG_VOLTAGE(pincfg)) {
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case IT8XXX2_VOLTAGE_3V3:
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/* Input voltage selection 3.3V. */
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*reg_volt_sel &= ~gpio->volt_sel_mask[pin];
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break;
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case IT8XXX2_VOLTAGE_1V8:
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__ASSERT(!(IT8XXX2_DT_PINCFG_PUPDR(pincfg)
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== IT8XXX2_PULL_UP),
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"Don't enable internal pullup if 1.8V voltage is used");
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/* Input voltage selection 1.8V. */
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*reg_volt_sel |= gpio->volt_sel_mask[pin];
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break;
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default:
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LOG_ERR("The voltage selection is not supported");
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return -EINVAL;
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}
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}
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/* Setting tri-state mode. */
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if (IT8XXX2_DT_PINCFG_IMPEDANCE(pincfg)) {
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*reg_gpcr |= (GPCR_PORT_PIN_MODE_PULLUP |
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GPCR_PORT_PIN_MODE_PULLDOWN);
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}
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/* Driving current selection. */
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if (reg_pdsc != NULL &&
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IT8XXX2_DT_PINCFG_DRIVE_CURRENT(pincfg) != IT8XXX2_DRIVE_DEFAULT) {
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if (IT8XXX2_DT_PINCFG_DRIVE_CURRENT(pincfg) & IT8XXX2_PDSCX_MASK) {
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/* Driving current selects low. */
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*reg_pdsc |= BIT(pin);
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} else {
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/* Driving current selects high. */
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*reg_pdsc &= ~BIT(pin);
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}
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}
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return 0;
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}
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static int pinctrl_gpio_it8xxx2_configure_pins(const pinctrl_soc_pin_t *pins)
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{
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const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
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const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio);
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uint8_t pin = pins->pin;
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volatile uint8_t *reg_gpcr = (uint8_t *)gpio->reg_gpcr + pin;
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volatile uint8_t *reg_func3_gcr = (uint8_t *)(gpio->func3_gcr[pin]);
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volatile uint8_t *reg_func4_gcr = (uint8_t *)(gpio->func4_gcr[pin]);
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volatile uint8_t *reg_func3_ext = (uint8_t *)(gpio->func3_ext[pin]);
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/* Handle PIN configuration. */
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if (pinctrl_it8xxx2_set(pins)) {
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LOG_ERR("Pin configuration is invalid.");
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return -EINVAL;
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}
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/*
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* Default input mode prevents leakage during changes to extended
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* setting (e.g. enabling i2c functionality on GPIO E1/E2 on IT82002)
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*/
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
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~GPCR_PORT_PIN_MODE_OUTPUT;
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/*
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* If pincfg is input, we don't need to handle
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* alternate function.
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*/
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if (IT8XXX2_DT_PINCFG_INPUT(pins->pincfg)) {
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return 0;
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}
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/*
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* Handle alternate function.
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*/
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if (reg_func3_gcr != NULL) {
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*reg_func3_gcr &= ~gpio->func3_en_mask[pin];
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}
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/* Ensure that func3-ext setting is in default state. */
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if (reg_func3_ext != NULL) {
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*reg_func3_ext &= ~gpio->func3_ext_mask[pin];
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}
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switch (pins->alt_func) {
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case IT8XXX2_ALT_FUNC_1:
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/* Func1: Alternate function will be set below. */
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break;
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case IT8XXX2_ALT_FUNC_2:
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/* Func2: WUI function: pin has been set as input above.*/
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return 0;
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case IT8XXX2_ALT_FUNC_3:
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/*
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* Func3: In addition to the alternate setting above,
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* Func3 also need to set the general control.
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*/
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if (reg_func3_gcr != NULL) {
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*reg_func3_gcr |= gpio->func3_en_mask[pin];
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}
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/* Func3-external: Some pins require external setting. */
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if (reg_func3_ext != NULL) {
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*reg_func3_ext |= gpio->func3_ext_mask[pin];
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}
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break;
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case IT8XXX2_ALT_FUNC_4:
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/*
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* Func4: In addition to the alternate setting above,
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* Func4 also need to set the general control.
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*/
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*reg_func4_gcr |= gpio->func4_en_mask[pin];
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break;
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case IT8XXX2_ALT_DEFAULT:
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*reg_func3_gcr &= ~gpio->func3_en_mask[pin];
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*reg_func4_gcr &= ~gpio->func4_en_mask[pin];
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return 0;
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default:
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LOG_ERR("This function is not supported.");
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return -EINVAL;
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}
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/* Common settings for alternate function. */
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*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_INPUT |
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GPCR_PORT_PIN_MODE_OUTPUT);
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return 0;
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}
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static int pinctrl_kscan_it8xxx2_set(const pinctrl_soc_pin_t *pins)
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{
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const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
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const struct pinctrl_it8xxx2_ksi_kso *ksi_kso = &(pinctrl_config->ksi_kso);
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volatile uint8_t *reg_ctrl = ksi_kso->reg_ctrl;
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uint8_t pullup_mask = ksi_kso->pullup_mask;
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uint8_t pp_od_mask = ksi_kso->pp_od_mask;
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uint32_t pincfg = pins->pincfg;
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/*
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* Enable or disable internal pull-up (this bit apply to all pins):
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* If KSI[7:0]/KSO[15:0] is in KBS mode , setting 1 enables the internal
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* pull-up (KSO[17:16] setting internal pull-up by GPIO port GPCR register).
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* If KSI[7:0]/KSO[15:0] is in GPIO mode, then this bit is always disabled.
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*/
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switch (IT8XXX2_DT_PINCFG_PULLUP(pincfg)) {
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case IT8XXX2_PULL_PIN_DEFAULT:
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/* Disable internal pulll-up */
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*reg_ctrl &= ~pullup_mask;
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break;
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case IT8XXX2_PULL_UP:
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*reg_ctrl |= pullup_mask;
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break;
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default:
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LOG_ERR("This pull level is not supported.");
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return -EINVAL;
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}
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/*
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* Set push-pull or open-drain mode (this bit apply to all pins):
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* KSI[7:0] doesn't support push-pull and open-drain settings in kbs mode.
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* If KSO[17:0] is in KBS mode, setting 1 selects open-drain mode,
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* setting 0 selects push-pull mode.
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* If KSO[15:0] is in GPIO mode, then this bit is always disabled.
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*/
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if (pp_od_mask != NO_FUNC) {
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switch (IT8XXX2_DT_PINCFG_PP_OD(pincfg)) {
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case IT8XXX2_PUSH_PULL:
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*reg_ctrl &= ~pp_od_mask;
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break;
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case IT8XXX2_OPEN_DRAIN:
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*reg_ctrl |= pp_od_mask;
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break;
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default:
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LOG_ERR("This pull mode is not supported.");
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return -EINVAL;
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}
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}
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return 0;
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}
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static int pinctrl_kscan_it8xxx2_configure_pins(const pinctrl_soc_pin_t *pins)
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{
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const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
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const struct pinctrl_it8xxx2_ksi_kso *ksi_kso = &(pinctrl_config->ksi_kso);
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/* Set a pin of KSI[7:0]/KSO[15:0] to pullup, push-pull/open-drain */
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if (pinctrl_kscan_it8xxx2_set(pins)) {
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return -EINVAL;
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}
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#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
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uint8_t pin_mask = BIT(pins->pin);
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volatile uint8_t *reg_gctrl = ksi_kso->reg_gctrl;
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switch (pins->alt_func) {
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case IT8XXX2_ALT_FUNC_1:
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/* Set a pin of KSI[7:0]/KSO[15:0] to kbs mode */
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*reg_gctrl &= ~pin_mask;
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break;
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case IT8XXX2_ALT_DEFAULT:
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/* Set a pin of KSI[7:0]/KSO[15:0] to gpio mode */
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*reg_gctrl |= pin_mask;
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break;
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#elif CONFIG_SOC_IT8XXX2_REG_SET_V2
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uint8_t pin = pins->pin;
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volatile uint8_t *reg_gctrl = ksi_kso->reg_gctrl + pin;
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switch (pins->alt_func) {
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case IT8XXX2_ALT_FUNC_1:
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/* Set a pin of KSI[7:0]/KSO[15:0] to kbs mode */
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*reg_gctrl &= ~(GPCR_PORT_PIN_MODE_INPUT |
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GPCR_PORT_PIN_MODE_OUTPUT);
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break;
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case IT8XXX2_ALT_DEFAULT:
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/* Set a pin of KSI[7:0]/KSO[15:0] to gpio mode */
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*reg_gctrl = (*reg_gctrl | GPCR_PORT_PIN_MODE_INPUT) &
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~GPCR_PORT_PIN_MODE_OUTPUT;
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break;
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#endif
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default:
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LOG_ERR("Alternate function not supported");
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return -ENOTSUP;
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}
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return 0;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
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ARG_UNUSED(reg);
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const struct pinctrl_it8xxx2_config *pinctrl_config;
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int status;
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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pinctrl_config = pins[i].pinctrls->config;
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if (pinctrl_config->gpio_group) {
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status = pinctrl_gpio_it8xxx2_configure_pins(&pins[i]);
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} else {
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status = pinctrl_kscan_it8xxx2_configure_pins(&pins[i]);
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}
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if (status < 0) {
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LOG_ERR("%s pin%d configuration is invalid.",
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pins[i].pinctrls->name, pins[i].pin);
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return status;
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}
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}
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return 0;
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}
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static int pinctrl_it8xxx2_init(const struct device *dev)
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{
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struct gpio_it8xxx2_regs *const gpio_base = GPIO_IT8XXX2_REG_BASE;
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/*
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* The default value of LPCRSTEN is bit2:1 = 10b(GPD2) in GCR.
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* If LPC reset is enabled on GPB7, we have to clear bit2:1
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* to 00b.
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*/
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gpio_base->GPIO_GCR &= ~IT8XXX2_GPIO_LPCRSTEN;
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#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
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#if defined(CONFIG_I2C_ITE_ENHANCE) && DT_NODE_HAS_STATUS(DT_NODELABEL(i2c5), okay)
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const struct gpio_dt_spec scl_gpios = GPIO_DT_SPEC_GET(DT_NODELABEL(i2c5), scl_gpios);
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const struct gpio_dt_spec sda_gpios = GPIO_DT_SPEC_GET(DT_NODELABEL(i2c5), sda_gpios);
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/*
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* When setting these pins as I2C alternate mode and then setting
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* GCR7 or func3-ext of GPIO extended, it will cause leakage.
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* In order to prevent leakage, it must be set to GPIO INPUT mode.
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*/
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/* Set I2C5 SCL as GPIO input to prevent leakage */
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gpio_pin_configure_dt(&scl_gpios, GPIO_INPUT);
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/* Set I2C5 SDA as GPIO input to prevent leakage */
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gpio_pin_configure_dt(&sda_gpios, GPIO_INPUT);
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#endif
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/*
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* Swap the default I2C2 SMCLK2/SMDAT2 pins from GPC7/GPD0 to GPF6/GPF7,
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* and I2C3 SMCLK3/SMDAT3 pins from GPB2/GPB5 to GPH1/GPH2,
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* and I2C5 SMCLK5/SMDAT5 pins from GPE1/GPE2 to GPA4/GPA5,
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*/
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gpio_base->GPIO_GCR7 &= ~(IT8XXX2_GPIO_SMB2PS |
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IT8XXX2_GPIO_SMB3PS |
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IT8XXX2_GPIO_SMB5PS);
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#endif
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return 0;
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}
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#define INIT_UNION_CONFIG(inst) \
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COND_CODE_1(DT_INST_PROP(inst, gpio_group), \
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(.gpio = { \
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.reg_gpcr = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
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.reg_pdsc = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 1), \
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.func3_gcr = DT_INST_PROP(inst, func3_gcr), \
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.func3_en_mask = DT_INST_PROP(inst, func3_en_mask), \
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.func3_ext = DT_INST_PROP_OR(inst, func3_ext, {0}), \
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.func3_ext_mask = DT_INST_PROP_OR(inst, func3_ext_mask, {0}), \
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.func4_gcr = DT_INST_PROP(inst, func4_gcr), \
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.func4_en_mask = DT_INST_PROP(inst, func4_en_mask), \
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.volt_sel = DT_INST_PROP(inst, volt_sel), \
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.volt_sel_mask = DT_INST_PROP(inst, volt_sel_mask), \
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}), \
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(.ksi_kso = { \
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.reg_gctrl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
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.reg_ctrl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 1), \
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.pp_od_mask = (uint8_t)DT_INST_PROP(inst, pp_od_mask), \
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.pullup_mask = (uint8_t)DT_INST_PROP(inst, pullup_mask), \
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}) \
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)
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#define PINCTRL_ITE_INIT(inst) \
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static const struct pinctrl_it8xxx2_config pinctrl_it8xxx2_cfg_##inst = { \
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.gpio_group = DT_INST_PROP(inst, gpio_group), \
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{ \
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INIT_UNION_CONFIG(inst) \
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} \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, &pinctrl_it8xxx2_init, \
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NULL, \
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NULL, \
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&pinctrl_it8xxx2_cfg_##inst, \
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PRE_KERNEL_1, \
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
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NULL);
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DT_INST_FOREACH_STATUS_OKAY(PINCTRL_ITE_INIT)
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