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zephyr/soc/xtensa
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Sathish Kuttan 66d0898a21 soc: intel_s1000: add audio master clock config 
Added a SOC level routine to configure master clock outputs
if CONFIG_AUDIO is defined.

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
 		2019-02-11 21:34:08 -05:00
..
D_108mini interrupts: simplify position of sw ISR table 2018-11-10 11:01:22 -05:00
D_212GP interrupts: simplify position of sw ISR table 2018-11-10 11:01:22 -05:00
D_233L interrupts: simplify position of sw ISR table 2018-11-10 11:01:22 -05:00
XRC_D2PM_5swIrq interrupts: simplify position of sw ISR table 2018-11-10 11:01:22 -05:00
XRC_FUSION_AON_ALL_LM interrupts: simplify position of sw ISR table 2018-11-10 11:01:22 -05:00
esp32 dts: xtensa: esp32: Add device tree support. 2019-01-29 09:47:17 -06:00
hifi2_std interrupts: simplify position of sw ISR table 2018-11-10 11:01:22 -05:00
hifi3_bd5 interrupts: simplify position of sw ISR table 2018-11-10 11:01:22 -05:00
hifi3_bd5_call0 interrupts: simplify position of sw ISR table 2018-11-10 11:01:22 -05:00
hifi4_bd7 interrupts: simplify position of sw ISR table 2018-11-10 11:01:22 -05:00
hifi_mini interrupts: simplify position of sw ISR table 2018-11-10 11:01:22 -05:00
hifi_mini_4swIrq interrupts: simplify position of sw ISR table 2018-11-10 11:01:22 -05:00
intel_s1000 soc: intel_s1000: add audio master clock config 2019-02-11 21:34:08 -05:00
sample_controller dts: qemu_xtensa/xt-sim: Enable device tree support 2019-02-01 07:49:28 -06:00