zephyr/boards/rak/rak4631/rak4631_nrf52840-pinctrl.dtsi

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/*
* Copyright (c) 2022 Nordic Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 20)>,
<NRF_PSEL(UART_RX, 0, 19)>;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 20)>,
<NRF_PSEL(UART_RX, 0, 19)>;
low-power-enable;
};
};
uart1_default: uart1_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 16)>,
<NRF_PSEL(UART_RX, 0, 15)>;
};
};
uart1_sleep: uart1_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 16)>,
<NRF_PSEL(UART_RX, 0, 15)>;
low-power-enable;
};
};
i2c0_default: i2c0_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 13)>,
<NRF_PSEL(TWIM_SCL, 0, 14)>;
};
};
i2c0_sleep: i2c0_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 13)>,
<NRF_PSEL(TWIM_SCL, 0, 14)>;
low-power-enable;
};
};
i2c1_default: i2c1_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 24)>,
<NRF_PSEL(TWIM_SCL, 0, 25)>;
};
};
i2c1_sleep: i2c1_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 24)>,
<NRF_PSEL(TWIM_SCL, 0, 25)>;
low-power-enable;
};
};
spi1_default: spi1_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 11)>,
<NRF_PSEL(SPIM_MOSI, 1, 12)>,
<NRF_PSEL(SPIM_MISO, 1, 13)>;
};
};
spi1_sleep: spi1_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 11)>,
<NRF_PSEL(SPIM_MOSI, 1, 12)>,
<NRF_PSEL(SPIM_MISO, 1, 13)>;
low-power-enable;
};
};
qspi_default: qspi_default {
group1 {
psels = <NRF_PSEL(QSPI_SCK, 0, 3)>,
<NRF_PSEL(QSPI_IO0, 0, 30)>,
<NRF_PSEL(QSPI_IO1, 0, 29)>,
<NRF_PSEL(QSPI_IO2, 0, 28)>,
<NRF_PSEL(QSPI_IO3, 0, 2)>,
<NRF_PSEL(QSPI_CSN, 0, 26)>;
};
};
qspi_sleep: qspi_sleep {
group1 {
psels = <NRF_PSEL(QSPI_SCK, 0, 3)>,
<NRF_PSEL(QSPI_IO0, 0, 30)>,
<NRF_PSEL(QSPI_IO1, 0, 29)>,
<NRF_PSEL(QSPI_IO2, 0, 28)>,
<NRF_PSEL(QSPI_IO3, 0, 2)>,
<NRF_PSEL(QSPI_CSN, 0, 26)>;
low-power-enable;
};
};
};