126 lines
3.5 KiB
Plaintext
126 lines
3.5 KiB
Plaintext
/*
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* Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH
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* Copyright (c) 2017 Linaro Limited
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* Copyright (c) 2023 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "reel_board_nrf52840_2-pinctrl.dtsi"
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/ {
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model = "reel board v2";
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compatible = "phytec,reel_board_v2";
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,uart-mcumgr = &uart0;
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zephyr,bt-mon-uart = &uart0;
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zephyr,bt-c2h-uart = &uart0;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,code-partition = &slot0_partition;
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zephyr,display = &ssd16xx;
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};
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aliases {
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watchdog0 = &wdt0;
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};
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mipi_dbi {
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compatible = "zephyr,mipi-dbi-spi";
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spi-dev = <&spi1>;
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reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
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dc-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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ssd16xx: ssd16xxfb@0 {
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compatible = "gooddisplay,gdeh0213b72", "solomon,ssd1675a";
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mipi-max-frequency = <4000000>;
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reg = <0>;
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width = <250>;
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height = <122>;
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busy-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
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full {
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gdv = [15];
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sdv = [41 a8 32];
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vcom = <0x26>;
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border-waveform = <0x03>;
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dummy-line = <0x30>;
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gate-line-width = <0x0a>;
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lut = [
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/*
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* Waveform Composition
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*
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* There are 7 Voltage Source (VS) Level groups
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* n = {0,1,2...6}, each group contains
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* 4 phases x = {A,B,C,D}.
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* 2 bits represent the voltage in a phase:
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* 00 – VSS, 01 – VSH1, 10 – VSL, 11 - VSH2
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*
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* For example 0x80 represents sequence VSL-VSS-VSS-VSS,
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*/
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80 60 40 00 00 00 00 /* LUT0: BB: VS 0..6 */
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10 60 20 00 00 00 00 /* LUT1: BW: VS 0..6 */
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80 60 40 00 00 00 00 /* LUT2: WB: VS 0..6 */
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10 60 20 00 00 00 00 /* LUT3: WW: VS 0..6 */
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00 00 00 00 00 00 00 /* LUT4: VCOM: VS 0..6 */
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/*
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* TPnx determines the length of each phase,
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* and RPn repeat count of a sequence.
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* TPnA, TPnB, TPnC, TPnD, RPn
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*
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* For example TP0A=3, TP0B=3, and RP0=2:
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* VS sequence : VSL-VSS-VSS-VSS
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* number of Gate Pulses (length) : 3 3 0 0
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* repeat count : 2
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*/
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03 03 00 00 02 /* TP0A TP0B TP0C TP0D RP0 */
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09 09 00 00 02 /* TP1A TP1B TP1C TP1D RP1 */
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03 03 00 00 02 /* TP2A TP2B TP2C TP2D RP2 */
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00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */
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00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */
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00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */
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00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */
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];
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};
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partial {
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gdv = [15];
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sdv = [41 a8 32];
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vcom = <0x26>;
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border-waveform = <0x01>;
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dummy-line = <0x30>;
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gate-line-width = <0x0a>;
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lut = [
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00 00 00 00 00 00 00 /* LUT0: BB: VS0..6 */
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80 00 00 00 00 00 00 /* LUT1: BW: VS0..6 */
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40 00 00 00 00 00 00 /* LUT2: WB: VS0..6 */
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80 00 00 00 00 00 00 /* LUT3: WW: VS0..6 */
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00 00 00 00 00 00 00 /* LUT4: VCOM: VS0..6 */
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0A 00 00 00 04 /* TP0A TP0B TP0C TP0D RP0 */
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00 00 00 00 00 /* TP1A TP1B TP1C TP1D RP1 */
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00 00 00 00 00 /* TP2A TP2B TP2C TP2D RP2 */
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00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */
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00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */
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00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */
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00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */
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];
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};
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};
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};
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};
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&spi1 {
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compatible = "nordic,nrf-spi";
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status = "okay";
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cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&spi1_default>;
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pinctrl-1 = <&spi1_sleep>;
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pinctrl-names = "default", "sleep";
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};
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