93 lines
3.2 KiB
ReStructuredText
93 lines
3.2 KiB
ReStructuredText
.. _nrf54l15bsim:
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NRF54L15 simulated boards (BabbleSim)
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#####################################
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.. contents::
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:depth: 1
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:backlinks: entry
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:local:
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Overview
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********
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To allow simulating nRF54L15 SOCs a Zephyr target boards is provided: the
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``nrf54l15bsim/nrf54l15/cpuapp``.
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This uses `BabbleSim`_ to simulate the radio activity, and the
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:ref:`POSIX architecture<Posix arch>` and the `native simulator`_ to
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run applications natively on the development system. This has the benefit of
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providing native code execution performance and easy debugging using
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native tools, but inherits :ref:`its limitations <posix_arch_limitations>`.
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Just like for the nrf54l15pdk target,
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the nrf54l15bsim/nrf54l15/cpuapp build target provides support for the application core,
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on the simulated nRF54L15 SOC.
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.. note::
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This simulated target does **not** yet support targeting the cpuflpr core.
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.. warning::
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This target is experimental, and even though it includes models of the RADIO, it does not yet
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include models of the AAR, CCM or ECB peripherals, so the BLE and 802.15.4 stacks can only be
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run without encryption or privacy features so far.
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This boards include models of some of the nRF54L15 SOC peripherals:
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* CLOCK (Clock control)
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* DPPI (Distributed Programmable Peripheral Interconnect)
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* EGU (Event Generator Unit)
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* FICR (Factory Information Configuration Registers)
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* GRTC (Global Real-time Counter)
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* PPIB (PPI Bridge)
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* RADIO
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* RRAMC (Resistive RAM Controller)
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* RTC (Real Time Counter)
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* TEMP (Temperature sensor)
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* TIMER
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* UICR (User Information Configuration Registers)
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and will use the same drivers as the nrf54l15pdk targets for these.
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For more information on what is modeled to which level of detail,
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check the `HW models implementation status`_.
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Note that unlike a real nrf54l15 device, the nrf54l15bsim boards have unlimited RAM, and code does
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not occupy their RRAM.
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.. _BabbleSim:
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https://BabbleSim.github.io
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.. _native simulator:
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https://github.com/BabbleSim/native_simulator/blob/main/docs/README.md
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.. _HW models implementation status:
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https://github.com/BabbleSim/ext_nRF_hw_models/blob/main/docs/README_impl_status.md
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Building for, and using this board
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**********************************
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You can follow the instructions from the :ref:`nrf52_bsim board <nrf52bsim_build_and_run>`.
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Simply change the board/target appropriately when building.
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TrustZone, TF-M and other security considerations
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*************************************************
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ARM's TrustZone is not modeled in this board. This means that:
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* There is no differentiation between secure and non secure execution states or bus accesses.
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* All RAM, flash and peripherals are in principle accessible from all SW. Peripherals with their
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own interconnect master ports can, in principle, access any other peripheral or RAM area.
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* There is no nrf54l15bsim/nrf54l15/cpuapp/ns board/build target, or possibility of mixing secure
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and non-secure images.
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* Currently there is no model of the SPU, and therefore neither RRAM, RAM areas or peripherals
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can be labeled as restricted for secure or non secure access.
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* TF-M cannot be used.
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Note that the CRACEN peripheral is not modeled. The mbedTLS library can still be used
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but with a SW crypto backend.
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