337 lines
8.6 KiB
C
337 lines
8.6 KiB
C
/*
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* Copyright (c) 2016 Freescale Semiconductor, Inc.
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* Copyright (c) 2017, NXP
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* Copyright (c) 2018 Foundries.io
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT openisa_rv32m1_gpio
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#include <errno.h>
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#include <device.h>
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#include <drivers/gpio.h>
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#include <soc.h>
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#include <fsl_common.h>
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#include <fsl_port.h>
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#include <drivers/clock_control.h>
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#include "gpio_utils.h"
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struct gpio_rv32m1_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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GPIO_Type *gpio_base;
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PORT_Type *port_base;
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unsigned int flags;
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const struct device *clock_dev;
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clock_control_subsys_t clock_subsys;
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int (*irq_config_func)(const struct device *dev);
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};
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struct gpio_rv32m1_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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/* port ISR callback routine address */
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sys_slist_t callbacks;
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};
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static uint32_t get_port_pcr_irqc_value_from_flags(const struct device *dev,
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uint32_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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port_interrupt_t port_interrupt = 0;
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if (mode == GPIO_INT_MODE_DISABLED) {
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port_interrupt = kPORT_InterruptOrDMADisabled;
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} else {
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if (mode == GPIO_INT_MODE_LEVEL) {
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if (trig == GPIO_INT_TRIG_LOW) {
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port_interrupt = kPORT_InterruptLogicZero;
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} else {
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port_interrupt = kPORT_InterruptLogicOne;
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}
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} else {
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switch (trig) {
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case GPIO_INT_TRIG_LOW:
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port_interrupt = kPORT_InterruptFallingEdge;
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break;
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case GPIO_INT_TRIG_HIGH:
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port_interrupt = kPORT_InterruptRisingEdge;
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break;
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case GPIO_INT_TRIG_BOTH:
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port_interrupt = kPORT_InterruptEitherEdge;
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break;
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}
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}
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}
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return PORT_PCR_IRQC(port_interrupt);
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}
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static int gpio_rv32m1_configure(const struct device *dev,
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gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_rv32m1_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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PORT_Type *port_base = config->port_base;
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uint32_t mask = 0U;
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uint32_t pcr = 0U;
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/* Check for an invalid pin number */
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if (pin >= ARRAY_SIZE(port_base->PCR)) {
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return -EINVAL;
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}
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/* Check for an invalid pin configuration */
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if ((flags & GPIO_INT_ENABLE) && ((flags & GPIO_INPUT) == 0)) {
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return -EINVAL;
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}
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if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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return -ENOTSUP;
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}
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/* Check if GPIO port supports interrupts */
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if ((flags & GPIO_INT_ENABLE) &&
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((config->flags & GPIO_INT_ENABLE) == 0U)) {
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return -ENOTSUP;
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}
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/* The flags contain options that require touching registers in the
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* GPIO module and the corresponding PORT module.
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*
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* Start with the GPIO module and set up the pin direction register.
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* 0 - pin is input, 1 - pin is output
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*/
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switch (flags & GPIO_DIR_MASK) {
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case GPIO_INPUT:
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gpio_base->PDDR &= ~BIT(pin);
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break;
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case GPIO_OUTPUT:
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
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gpio_base->PSOR = BIT(pin);
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
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gpio_base->PCOR = BIT(pin);
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}
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gpio_base->PDDR |= BIT(pin);
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break;
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default:
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return -ENOTSUP;
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}
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/* Now do the PORT module. Figure out the pullup/pulldown
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* configuration, but don't write it to the PCR register yet.
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*/
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mask |= PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
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if ((flags & GPIO_PULL_UP) != 0) {
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/* Enable the pull and select the pullup resistor. */
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pcr |= PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
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} else if ((flags & GPIO_PULL_DOWN) != 0) {
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/* Enable the pull and select the pulldown resistor (deselect
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* the pullup resistor.
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*/
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pcr |= PORT_PCR_PE_MASK;
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}
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/* Still in the PORT module. Figure out the interrupt configuration,
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* but don't write it to the PCR register yet.
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*/
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mask |= PORT_PCR_IRQC_MASK;
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/* Accessing by pin, we only need to write one PCR register. */
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port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr;
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return 0;
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}
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static int gpio_rv32m1_port_get_raw(const struct device *dev, uint32_t *value)
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{
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const struct gpio_rv32m1_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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*value = gpio_base->PDIR;
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return 0;
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}
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static int gpio_rv32m1_port_set_masked_raw(const struct device *dev,
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uint32_t mask,
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uint32_t value)
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{
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const struct gpio_rv32m1_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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gpio_base->PDOR = (gpio_base->PDOR & ~mask) | (mask & value);
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return 0;
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}
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static int gpio_rv32m1_port_set_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_rv32m1_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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gpio_base->PSOR = mask;
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return 0;
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}
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static int gpio_rv32m1_port_clear_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_rv32m1_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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gpio_base->PCOR = mask;
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return 0;
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}
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static int gpio_rv32m1_port_toggle_bits(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_rv32m1_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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gpio_base->PTOR = mask;
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return 0;
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}
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static int gpio_rv32m1_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_rv32m1_config *config = dev->config;
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PORT_Type *port_base = config->port_base;
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/* Check for an invalid pin number */
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if (pin >= ARRAY_SIZE(port_base->PCR)) {
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return -EINVAL;
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}
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/* Check if GPIO port supports interrupts */
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if ((mode != GPIO_INT_MODE_DISABLED) &&
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((config->flags & GPIO_INT_ENABLE) == 0U)) {
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return -ENOTSUP;
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}
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uint32_t pcr = get_port_pcr_irqc_value_from_flags(dev, pin, mode, trig);
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port_base->PCR[pin] = (port_base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | pcr;
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return 0;
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}
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static int gpio_rv32m1_manage_callback(const struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_rv32m1_data *data = dev->data;
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gpio_manage_callback(&data->callbacks, callback, set);
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return 0;
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}
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static void gpio_rv32m1_port_isr(const struct device *dev)
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{
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const struct gpio_rv32m1_config *config = dev->config;
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struct gpio_rv32m1_data *data = dev->data;
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uint32_t int_status;
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int_status = config->port_base->ISFR;
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/* Clear the port interrupts before invoking callbacks */
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config->port_base->ISFR = int_status;
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gpio_fire_callbacks(&data->callbacks, dev, int_status);
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}
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static int gpio_rv32m1_init(const struct device *dev)
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{
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const struct gpio_rv32m1_config *config = dev->config;
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int ret;
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if (config->clock_dev) {
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ret = clock_control_on(config->clock_dev, config->clock_subsys);
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if (ret < 0) {
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return ret;
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}
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}
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return config->irq_config_func(dev);
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}
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static const struct gpio_driver_api gpio_rv32m1_driver_api = {
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.pin_configure = gpio_rv32m1_configure,
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.port_get_raw = gpio_rv32m1_port_get_raw,
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.port_set_masked_raw = gpio_rv32m1_port_set_masked_raw,
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.port_set_bits_raw = gpio_rv32m1_port_set_bits_raw,
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.port_clear_bits_raw = gpio_rv32m1_port_clear_bits_raw,
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.port_toggle_bits = gpio_rv32m1_port_toggle_bits,
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.pin_interrupt_configure = gpio_rv32m1_pin_interrupt_configure,
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.manage_callback = gpio_rv32m1_manage_callback,
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};
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#define INST_DT_PORT_ADDR(n) \
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DT_REG_ADDR(DT_INST_PHANDLE(n, openisa_rv32m1_port))
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#define INST_DT_CLK_CTRL_DEV(n) \
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UTIL_AND(DT_INST_NODE_HAS_PROP(n, clocks), DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)))
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#define INST_DT_CLK_CELL_NAME(n) \
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UTIL_AND(DT_INST_NODE_HAS_PROP(n, clocks), DT_INST_CLOCKS_CELL(n, name))
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#define GPIO_RV32M1_INIT(n) \
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static int gpio_rv32m1_##n##_init(const struct device *dev); \
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\
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static const struct gpio_rv32m1_config gpio_rv32m1_##n##_config = {\
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.common = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
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}, \
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.gpio_base = (GPIO_Type *) DT_INST_REG_ADDR(n), \
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.port_base = (PORT_Type *) INST_DT_PORT_ADDR(n), \
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.flags = GPIO_INT_ENABLE, \
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.irq_config_func = gpio_rv32m1_##n##_init, \
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.clock_dev = INST_DT_CLK_CTRL_DEV(n), \
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.clock_subsys = (clock_control_subsys_t) \
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INST_DT_CLK_CELL_NAME(n) \
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}; \
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\
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static struct gpio_rv32m1_data gpio_rv32m1_##n##_data; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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gpio_rv32m1_init, \
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NULL, \
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&gpio_rv32m1_##n##_data, \
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&gpio_rv32m1_##n##_config, \
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PRE_KERNEL_1, \
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CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_rv32m1_driver_api); \
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\
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static int gpio_rv32m1_##n##_init(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), \
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0, \
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gpio_rv32m1_port_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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\
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irq_enable(DT_INST_IRQN(0)); \
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\
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return 0; \
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}
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DT_INST_FOREACH_STATUS_OKAY(GPIO_RV32M1_INIT)
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