539 lines
14 KiB
C
539 lines
14 KiB
C
/*
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*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_utils.h>
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#include <stm32_ll_system.h>
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#include <drivers/clock_control.h>
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#include <sys/util.h>
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#include <stm32_ll_utils.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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/* Macros to fill up prescaler values */
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#define z_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
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#define ahb_prescaler(v) z_ahb_prescaler(v)
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#define z_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v
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#define apb1_prescaler(v) z_apb1_prescaler(v)
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#define z_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v
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#define apb2_prescaler(v) z_apb2_prescaler(v)
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#define z_apb3_prescaler(v) LL_RCC_APB3_DIV_ ## v
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#define apb3_prescaler(v) z_apb3_prescaler(v)
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#if STM32_SYSCLK_SRC_PLL
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/**
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* @brief fill in pll configuration structure
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*/
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static void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
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{
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pllinit->PLLM = STM32_PLL_M_DIVISOR;
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pllinit->PLLN = STM32_PLL_N_MULTIPLIER;
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pllinit->PLLR = STM32_PLL_R_DIVISOR;
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}
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#endif /* STM32_SYSCLK_SRC_PLL */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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/* Enable the power interface clock */
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
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#if STM32_LSE_CLOCK
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if (!LL_PWR_IsEnabledBkUpAccess()) {
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/* Enable write access to Backup domain */
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LL_PWR_EnableBkUpAccess();
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while (!LL_PWR_IsEnabledBkUpAccess()) {
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/* Wait for Backup domain access */
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}
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}
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/* Enable LSE Oscillator */
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LL_RCC_LSE_Enable();
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/* Wait for LSE ready */
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while (!LL_RCC_LSE_IsReady()) {
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}
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/* Enable LSESYS additionnally */
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SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
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/* Wait till LSESYS is ready */
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while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U) {
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}
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LL_PWR_DisableBkUpAccess();
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#endif /* STM32_LSE_CLOCK */
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}
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/**
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* @brief fill in AHB/APB buses configuration structure
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*/
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static void config_bus_clk_init(LL_UTILS_ClkInitTypeDef *clk_init)
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{
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clk_init->AHBCLKDivider = ahb_prescaler(STM32_AHB_PRESCALER);
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clk_init->APB1CLKDivider = apb1_prescaler(STM32_APB1_PRESCALER);
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clk_init->APB2CLKDivider = apb2_prescaler(STM32_APB2_PRESCALER);
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clk_init->APB3CLKDivider = apb3_prescaler(STM32_APB3_PRESCALER);
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}
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static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
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{
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return clock / prescaler;
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}
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static inline int stm32_clock_control_on(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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ARG_UNUSED(dev);
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switch (pclken->bus) {
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case STM32_CLOCK_BUS_AHB1:
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LL_AHB1_GRP1_EnableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_AHB2:
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LL_AHB2_GRP1_EnableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_AHB3:
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LL_AHB3_GRP1_EnableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB1:
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LL_APB1_GRP1_EnableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB1_2:
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LL_APB1_GRP2_EnableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB2:
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LL_APB2_GRP1_EnableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB3:
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LL_APB3_GRP1_EnableClock(pclken->enr);
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static inline int stm32_clock_control_off(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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ARG_UNUSED(dev);
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switch (pclken->bus) {
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case STM32_CLOCK_BUS_AHB1:
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LL_AHB1_GRP1_DisableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_AHB2:
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LL_AHB2_GRP1_DisableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_AHB3:
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LL_AHB3_GRP1_DisableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB1:
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LL_APB1_GRP1_DisableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB1_2:
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LL_APB1_GRP2_DisableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB2:
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LL_APB2_GRP1_DisableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB3:
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LL_APB3_GRP1_DisableClock(pclken->enr);
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static int stm32_clock_control_get_subsys_rate(const struct device *dev,
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clock_control_subsys_t sys,
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uint32_t *rate)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sys);
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/*
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* Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)
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* SystemCoreClock is preferred to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
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* since it will be updated after clock configuration and hence
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* more likely to contain actual clock speed
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*/
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uint32_t ahb_clock = SystemCoreClock;
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uint32_t apb1_clock = get_bus_clock(ahb_clock, STM32_APB1_PRESCALER);
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uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_APB2_PRESCALER);
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uint32_t apb3_clock = get_bus_clock(ahb_clock, STM32_APB3_PRESCALER);
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ARG_UNUSED(dev);
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switch (pclken->bus) {
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case STM32_CLOCK_BUS_AHB1:
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case STM32_CLOCK_BUS_AHB2:
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case STM32_CLOCK_BUS_AHB3:
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*rate = ahb_clock;
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break;
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case STM32_CLOCK_BUS_APB1:
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case STM32_CLOCK_BUS_APB1_2:
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*rate = apb1_clock;
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break;
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case STM32_CLOCK_BUS_APB2:
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*rate = apb2_clock;
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break;
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case STM32_CLOCK_BUS_APB3:
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*rate = apb3_clock;
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static struct clock_control_driver_api stm32_clock_control_api = {
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.on = stm32_clock_control_on,
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.off = stm32_clock_control_off,
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.get_rate = stm32_clock_control_get_subsys_rate,
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};
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static void set_regu_voltage(uint32_t hclk_freq)
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{
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if (hclk_freq < MHZ(25)) {
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LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE4);
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} else if (hclk_freq < MHZ(55)) {
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LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE3);
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} else if (hclk_freq < MHZ(110)) {
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LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
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} else {
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LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
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}
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while (LL_PWR_IsActiveFlag_VOS() == 0) {
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}
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}
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/*
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* Unconditionally switch the system clock source to HSI.
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*/
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__unused
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static void clock_switch_to_hsi(uint32_t ahb_prescaler)
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{
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/* Enable HSI if not enabled */
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if (LL_RCC_HSI_IsReady() != 1) {
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/* Enable HSI */
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LL_RCC_HSI_Enable();
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while (LL_RCC_HSI_IsReady() != 1) {
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/* Wait for HSI ready */
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}
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}
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/* Set HSI as SYSCLCK source */
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
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LL_RCC_SetAHBPrescaler(ahb_prescaler);
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
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}
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}
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#if STM32_SYSCLK_SRC_MSIS || STM32_PLL_SRC_MSIS
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__unused
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static void set_up_clk_msis(void)
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{
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/* Set MSIS Range */
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LL_RCC_MSI_EnableRangeSelection();
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LL_RCC_MSIS_SetRange(STM32_MSIS_RANGE << RCC_ICSCR1_MSISRANGE_Pos);
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#if STM32_MSIS_PLL_MODE
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#if !STM32_LSE_CLOCK
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#error "MSI Hardware auto calibration requires LSE clock activation"
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#endif
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/* Enable MSI hardware auto calibration */
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LL_RCC_MSI_EnablePLLMode();
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#endif
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/* Set MSIS Range */
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LL_RCC_MSIS_Enable();
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/* Wait till MSIS is ready */
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while (LL_RCC_MSIS_IsReady() != 1) {
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}
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}
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#endif /* STM32_SYSCLK_SRC_MSIS || STM32_PLL_SRC_MSIS */
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#if STM32_SYSCLK_SRC_PLL
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/*
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* Configure PLL as source of SYSCLK
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*/
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void config_src_sysclk_pll(LL_UTILS_ClkInitTypeDef s_ClkInitStruct)
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{
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LL_UTILS_PLLInitTypeDef s_PLLInitStruct;
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/* configure PLL input settings */
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config_pll_init(&s_PLLInitStruct);
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/*
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* Switch to HSI and disable the PLL before configuration.
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* (Switching to HSI makes sure we have a SYSCLK source in
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* case we're currently running from the PLL we're about to
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* turn off and reconfigure.)
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*
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* Don't use s_ClkInitStruct.AHBCLKDivider as the AHB
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* prescaler here. In this configuration, that's the value to
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* use when the SYSCLK source is the PLL, not HSI.
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*/
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clock_switch_to_hsi(LL_RCC_SYSCLK_DIV_1);
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LL_RCC_PLL1_Disable();
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#if STM32_PLL_Q_DIVISOR
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LL_RCC_PLL1_SetQ(STM32_PLL_Q_DIVISOR);
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#endif /* STM32_PLL_Q_DIVISOR */
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set_regu_voltage(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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#if STM32_PLL_SRC_MSIS
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set_up_clk_msis();
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/* Switch to PLL with MSI as clock source */
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LL_PLL_ConfigSystemClock_MSI(&s_PLLInitStruct, &s_ClkInitStruct);
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/* Disable other clocks */
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LL_RCC_HSI_Disable();
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LL_RCC_HSE_Disable();
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#elif STM32_PLL_SRC_HSI
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/* Switch to PLL with HSI as clock source */
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LL_PLL_ConfigSystemClock_HSI(&s_PLLInitStruct, &s_ClkInitStruct);
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/* Disable other clocks */
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LL_RCC_HSE_Disable();
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LL_RCC_MSIS_Disable();
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#elif STM32_PLL_SRC_HSE
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int hse_bypass;
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if (IS_ENABLED(STM32_HSE_BYPASS)) {
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hse_bypass = LL_UTILS_HSEBYPASS_ON;
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} else {
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hse_bypass = LL_UTILS_HSEBYPASS_OFF;
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}
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/* Switch to PLL with HSE as clock source */
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LL_PLL1_ConfigSystemClock_HSE(CONFIG_CLOCK_STM32_HSE_CLOCK,
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hse_bypass,
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&s_PLLInitStruct,
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&s_ClkInitStruct);
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/* Disable other clocks */
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LL_RCC_HSI_Disable();
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LL_RCC_MSIS_Disable();
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#endif /* STM32_PLL_SRC_* */
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}
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#endif /* STM32_SYSCLK_SRC_PLL */
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#if STM32_SYSCLK_SRC_HSE
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/*
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* Configure HSE as source of SYSCLK
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*/
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void config_src_sysclk_hse(LL_UTILS_ClkInitTypeDef s_ClkInitStruct)
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{
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uint32_t old_hclk_freq;
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uint32_t new_hclk_freq;
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old_hclk_freq = HAL_RCC_GetHCLKFreq();
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/* Calculate new SystemCoreClock variable based on HSE freq */
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new_hclk_freq = __LL_RCC_CALC_HCLK_FREQ(CONFIG_CLOCK_STM32_HSE_CLOCK,
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s_ClkInitStruct.AHBCLKDivider);
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__ASSERT(new_hclk_freq == CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
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"Config mismatch HCLK frequency %u %u",
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, new_hclk_freq);
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/* If freq increases, set flash latency before any clock setting */
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if (new_hclk_freq > old_hclk_freq) {
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LL_SetFlashLatency(new_hclk_freq);
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}
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/* Enable HSE if not enabled */
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if (LL_RCC_HSE_IsReady() != 1) {
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/* Check if need to enable HSE bypass feature or not */
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if (IS_ENABLED(STM32_HSE_BYPASS)) {
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LL_RCC_HSE_EnableBypass();
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} else {
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LL_RCC_HSE_DisableBypass();
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}
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/* Enable HSE */
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LL_RCC_HSE_Enable();
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while (LL_RCC_HSE_IsReady() != 1) {
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/* Wait for HSE ready */
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}
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}
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/* Set HSE as SYSCLCK source */
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
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LL_RCC_SetAHBPrescaler(s_ClkInitStruct.AHBCLKDivider);
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
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}
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/* Update SystemCoreClock variable */
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LL_SetSystemCoreClock(new_hclk_freq);
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/* Set peripheral busses prescalers */
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LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
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LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider);
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LL_RCC_SetAPB3Prescaler(s_ClkInitStruct.APB3CLKDivider);
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/* If freq not increased, set flash latency after all clock setting */
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if (new_hclk_freq <= old_hclk_freq) {
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LL_SetFlashLatency(new_hclk_freq);
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}
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/* Disable other clocks */
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LL_RCC_HSI_Disable();
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LL_RCC_MSIS_Disable();
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LL_RCC_PLL1_Disable();
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}
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#endif /* STM32_SYSCLK_SRC_HSE */
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#if STM32_SYSCLK_SRC_MSIS
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/*
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* Configure MSI as source of SYSCLK
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*/
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void config_src_sysclk_msis(LL_UTILS_ClkInitTypeDef s_ClkInitStruct)
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{
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uint32_t old_hclk_freq;
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uint32_t new_hclk_freq;
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old_hclk_freq = HAL_RCC_GetHCLKFreq();
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/* Calculate new SystemCoreClock variable with MSI freq */
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/* MSI freq is defined from RUN range selection */
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new_hclk_freq = __LL_RCC_CALC_HCLK_FREQ(
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__LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSIRANGESEL_RUN,
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STM32_MSIS_RANGE << RCC_ICSCR1_MSISRANGE_Pos),
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s_ClkInitStruct.AHBCLKDivider);
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__ASSERT(new_hclk_freq == CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
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"Config mismatch HCLK frequency %u %u",
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, new_hclk_freq);
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/* If freq increases, set flash latency before any clock setting */
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if (new_hclk_freq > old_hclk_freq) {
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LL_SetFlashLatency(new_hclk_freq);
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}
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set_regu_voltage(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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/* Set MSIS as SYSCLCK source */
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set_up_clk_msis();
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_MSIS);
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LL_RCC_SetAHBPrescaler(s_ClkInitStruct.AHBCLKDivider);
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSIS) {
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}
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/* Update SystemCoreClock variable */
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LL_SetSystemCoreClock(new_hclk_freq);
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/* Set peripheral busses prescalers */
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LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
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LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider);
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LL_RCC_SetAPB3Prescaler(s_ClkInitStruct.APB3CLKDivider);
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/* If freq not increased, set flash latency after all clock setting */
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if (new_hclk_freq <= old_hclk_freq) {
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LL_SetFlashLatency(new_hclk_freq);
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}
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/* Disable other clocks */
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LL_RCC_HSE_Disable();
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LL_RCC_HSI_Disable();
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LL_RCC_PLL1_Disable();
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}
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#endif /* STM32_SYSCLK_SRC_MSIS */
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#if STM32_SYSCLK_SRC_HSI
|
|
/*
|
|
* Configure HSI as source of SYSCLK
|
|
*/
|
|
void config_src_sysclk_hsi(LL_UTILS_ClkInitTypeDef s_ClkInitStruct)
|
|
{
|
|
clock_switch_to_hsi(s_ClkInitStruct.AHBCLKDivider);
|
|
|
|
/* Update SystemCoreClock variable */
|
|
LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(HSI_VALUE,
|
|
s_ClkInitStruct.AHBCLKDivider));
|
|
|
|
/* Set peripheral busses prescalers */
|
|
LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
|
|
LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider);
|
|
LL_RCC_SetAPB3Prescaler(s_ClkInitStruct.APB3CLKDivider);
|
|
|
|
/* Set flash latency */
|
|
/* HSI used as SYSCLK, set latency to 0 */
|
|
LL_FLASH_SetLatency(LL_FLASH_LATENCY_0);
|
|
|
|
/* Disable other clocks */
|
|
LL_RCC_HSE_Disable();
|
|
LL_RCC_MSIS_Disable();
|
|
LL_RCC_PLL1_Disable();
|
|
}
|
|
#endif /* STM32_SYSCLK_SRC_HSI */
|
|
|
|
int stm32_clock_control_init(const struct device *dev)
|
|
{
|
|
LL_UTILS_ClkInitTypeDef s_ClkInitStruct;
|
|
|
|
ARG_UNUSED(dev);
|
|
|
|
/* configure clock for AHB/APB buses */
|
|
config_bus_clk_init((LL_UTILS_ClkInitTypeDef *)&s_ClkInitStruct);
|
|
|
|
/* Some clocks would be activated by default */
|
|
config_enable_default_clocks();
|
|
|
|
#if STM32_SYSCLK_SRC_PLL
|
|
/* Configure PLL as source of SYSCLK */
|
|
config_src_sysclk_pll(s_ClkInitStruct);
|
|
#elif STM32_SYSCLK_SRC_HSE
|
|
/* Configure HSE as source of SYSCLK */
|
|
config_src_sysclk_hse(s_ClkInitStruct);
|
|
#elif STM32_SYSCLK_SRC_MSIS
|
|
/* Configure MSIS as source of SYSCLK */
|
|
config_src_sysclk_msis(s_ClkInitStruct);
|
|
#elif STM32_SYSCLK_SRC_HSI
|
|
/* Configure HSI as source of SYSCLK */
|
|
config_src_sysclk_hsi(s_ClkInitStruct);
|
|
#endif /* STM32_SYSCLK_SRC_PLL... */
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* @brief RCC device, note that priority is intentionally set to 1 so
|
|
* that the device init runs just after SOC init
|
|
*/
|
|
DEVICE_DT_DEFINE(DT_NODELABEL(rcc),
|
|
&stm32_clock_control_init,
|
|
NULL,
|
|
NULL, NULL,
|
|
PRE_KERNEL_1,
|
|
CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
|
|
&stm32_clock_control_api);
|