396 lines
10 KiB
C
396 lines
10 KiB
C
/*
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* Copyright (c) 2020, Seagate Technology LLC
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_lpc11u6x_syscon
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#include <devicetree.h>
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#include <device.h>
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#include <drivers/clock_control/lpc11u6x_clock_control.h>
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#include <drivers/pinmux.h>
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#include "clock_control_lpc11u6x.h"
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static void syscon_power_up(struct lpc11u6x_syscon_regs *syscon,
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uint32_t bit, bool enable)
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{
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if (enable) {
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syscon->pd_run_cfg = (syscon->pd_run_cfg & ~bit)
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| LPC11U6X_PDRUNCFG_MASK;
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} else {
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syscon->pd_run_cfg = syscon->pd_run_cfg | bit
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| LPC11U6X_PDRUNCFG_MASK;
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}
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}
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static void syscon_set_pll_src(struct lpc11u6x_syscon_regs *syscon,
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uint32_t src)
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{
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syscon->sys_pll_clk_sel = src;
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syscon->sys_pll_clk_uen = 0;
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syscon->sys_pll_clk_uen = 1;
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}
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static void set_flash_access_time(uint32_t nr_cycles)
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{
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uint32_t *reg = (uint32_t *) LPC11U6X_FLASH_TIMING_REG;
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*reg = (*reg & (~LPC11U6X_FLASH_TIMING_MASK)) | nr_cycles;
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}
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static void syscon_setup_pll(struct lpc11u6x_syscon_regs *syscon,
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uint32_t msel, uint32_t psel)
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{
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uint32_t val = msel & LPC11U6X_SYS_PLL_CTRL_MSEL_MASK;
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val |= (psel & LPC11U6X_SYS_PLL_CTRL_PSEL_MASK) <<
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LPC11U6X_SYS_PLL_CTRL_PSEL_SHIFT;
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syscon->sys_pll_ctrl = val;
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}
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static bool syscon_pll_locked(struct lpc11u6x_syscon_regs *syscon)
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{
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return (syscon->sys_pll_stat & 0x1) != 0;
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}
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static void syscon_set_main_clock_source(struct lpc11u6x_syscon_regs *syscon,
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uint32_t src)
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{
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syscon->main_clk_sel = src;
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syscon->main_clk_uen = 0;
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syscon->main_clk_uen = 1;
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}
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static void syscon_ahb_clock_enable(struct lpc11u6x_syscon_regs *syscon,
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uint32_t mask, bool enable)
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{
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if (enable) {
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syscon->sys_ahb_clk_ctrl |= mask;
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} else {
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syscon->sys_ahb_clk_ctrl &= ~mask;
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}
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}
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#if defined(CONFIG_CLOCK_CONTROL_LPC11U6X_PLL_SRC_SYSOSC) \
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&& DT_INST_NODE_HAS_PROP(0, pinmuxs)
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/**
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* @brief: configure system oscillator pins.
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*
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* This system oscillator pins and their configurations are retrieved from the
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* "pinmuxs" property of the DT clock controller node.
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*/
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static void pinmux_enable_sysosc(void)
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{
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const struct device *pinmux_dev;
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uint32_t pin, func;
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pinmux_dev = device_get_binding(
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DT_LABEL(DT_INST_PHANDLE_BY_NAME(0, pinmuxs, xtalin)));
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if (!pinmux_dev) {
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return;
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}
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pin = DT_INST_PHA_BY_NAME(0, pinmuxs, xtalin, pin);
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func = DT_INST_PHA_BY_NAME(0, pinmuxs, xtalin, function);
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pinmux_pin_set(pinmux_dev, pin, func);
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pinmux_dev = device_get_binding(
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DT_LABEL(DT_INST_PHANDLE_BY_NAME(0, pinmuxs, xtalout)));
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if (!pinmux_dev) {
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return;
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}
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pin = DT_INST_PHA_BY_NAME(0, pinmuxs, xtalout, pin);
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func = DT_INST_PHA_BY_NAME(0, pinmuxs, xtalout, function);
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pinmux_pin_set(pinmux_dev, pin, func);
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}
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#else
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#define pinmux_enable_sysosc() do { } while (0)
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#endif
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static void syscon_peripheral_reset(struct lpc11u6x_syscon_regs *syscon,
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uint32_t mask, bool reset)
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{
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if (reset) {
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syscon->p_reset_ctrl &= ~mask;
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} else {
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syscon->p_reset_ctrl |= mask;
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}
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}
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static void syscon_frg_init(struct lpc11u6x_syscon_regs *syscon)
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{
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uint32_t div;
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div = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / LPC11U6X_USART_CLOCK_RATE;
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if (!div) {
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div = 1;
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}
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syscon->frg_clk_div = div;
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syscon_peripheral_reset(syscon, LPC11U6X_PRESET_CTRL_FRG, false);
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syscon->uart_frg_div = 0xFF;
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syscon->uart_frg_mult = ((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / div)
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* 256) / LPC11U6X_USART_CLOCK_RATE;
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}
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static void syscon_frg_deinit(struct lpc11u6x_syscon_regs *syscon)
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{
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syscon->uart_frg_div = 0x0;
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syscon_peripheral_reset(syscon, LPC11U6X_PRESET_CTRL_FRG, true);
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}
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static int lpc11u6x_clock_control_on(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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const struct lpc11u6x_syscon_config *cfg = dev->config;
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struct lpc11u6x_syscon_data *data = dev->data;
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uint32_t clk_mask = 0, reset_mask = 0;
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int ret = 0, init_frg = 0;
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k_mutex_lock(&data->mutex, K_FOREVER);
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switch ((int) sub_system) {
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case LPC11U6X_CLOCK_I2C0:
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clk_mask = LPC11U6X_SYS_AHB_CLK_CTRL_I2C0;
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reset_mask = LPC11U6X_PRESET_CTRL_I2C0;
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break;
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case LPC11U6X_CLOCK_I2C1:
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clk_mask = LPC11U6X_SYS_AHB_CLK_CTRL_I2C1;
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reset_mask = LPC11U6X_PRESET_CTRL_I2C1;
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break;
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case LPC11U6X_CLOCK_GPIO:
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clk_mask = LPC11U6X_SYS_AHB_CLK_CTRL_GPIO |
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LPC11U6X_SYS_AHB_CLK_CTRL_PINT;
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break;
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case LPC11U6X_CLOCK_USART0:
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cfg->syscon->usart0_clk_div = 1;
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clk_mask = LPC11U6X_SYS_AHB_CLK_CTRL_USART0;
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break;
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case LPC11U6X_CLOCK_USART1:
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if (!data->frg_in_use++) {
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init_frg = 1;
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}
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clk_mask = LPC11U6X_SYS_AHB_CLK_CTRL_USART1;
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reset_mask = LPC11U6X_PRESET_CTRL_USART1;
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break;
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case LPC11U6X_CLOCK_USART2:
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if (!data->frg_in_use++) {
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init_frg = 1;
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}
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clk_mask = LPC11U6X_SYS_AHB_CLK_CTRL_USART2;
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reset_mask = LPC11U6X_PRESET_CTRL_USART2;
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break;
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case LPC11U6X_CLOCK_USART3:
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if (!data->frg_in_use++) {
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init_frg = 1;
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}
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data->usart34_in_use++;
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clk_mask = LPC11U6X_SYS_AHB_CLK_CTRL_USART3_4;
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reset_mask = LPC11U6X_PRESET_CTRL_USART3;
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break;
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case LPC11U6X_CLOCK_USART4:
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if (!data->frg_in_use++) {
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init_frg = 1;
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}
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data->usart34_in_use++;
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clk_mask = LPC11U6X_SYS_AHB_CLK_CTRL_USART3_4;
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reset_mask = LPC11U6X_PRESET_CTRL_USART4;
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break;
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default:
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k_mutex_unlock(&data->mutex);
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return -EINVAL;
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}
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syscon_ahb_clock_enable(cfg->syscon, clk_mask, true);
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if (init_frg) {
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syscon_frg_init(cfg->syscon);
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}
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syscon_peripheral_reset(cfg->syscon, reset_mask, false);
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k_mutex_unlock(&data->mutex);
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return ret;
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}
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static int lpc11u6x_clock_control_off(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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const struct lpc11u6x_syscon_config *cfg = dev->config;
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struct lpc11u6x_syscon_data *data = dev->data;
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uint32_t clk_mask = 0, reset_mask = 0;
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int ret = 0, deinit_frg = 0;
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k_mutex_lock(&data->mutex, K_FOREVER);
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switch ((int) sub_system) {
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case LPC11U6X_CLOCK_I2C0:
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clk_mask = LPC11U6X_SYS_AHB_CLK_CTRL_I2C0;
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reset_mask = LPC11U6X_PRESET_CTRL_I2C0;
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break;
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case LPC11U6X_CLOCK_I2C1:
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clk_mask = LPC11U6X_SYS_AHB_CLK_CTRL_I2C1;
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reset_mask = LPC11U6X_PRESET_CTRL_I2C1;
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break;
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case LPC11U6X_CLOCK_GPIO:
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clk_mask = LPC11U6X_SYS_AHB_CLK_CTRL_GPIO |
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LPC11U6X_SYS_AHB_CLK_CTRL_PINT;
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break;
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case LPC11U6X_CLOCK_USART0:
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cfg->syscon->usart0_clk_div = 0;
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clk_mask = LPC11U6X_SYS_AHB_CLK_CTRL_USART0;
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break;
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case LPC11U6X_CLOCK_USART1:
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if (!(--data->frg_in_use)) {
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deinit_frg = 1;
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}
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clk_mask = LPC11U6X_SYS_AHB_CLK_CTRL_USART1;
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reset_mask = LPC11U6X_PRESET_CTRL_USART1;
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break;
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case LPC11U6X_CLOCK_USART2:
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if (!(--data->frg_in_use)) {
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deinit_frg = 1;
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}
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clk_mask = LPC11U6X_SYS_AHB_CLK_CTRL_USART2;
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reset_mask = LPC11U6X_PRESET_CTRL_USART2;
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break;
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case LPC11U6X_CLOCK_USART3:
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if (!(--data->frg_in_use)) {
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deinit_frg = 1;
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}
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if (!(--data->usart34_in_use)) {
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clk_mask = LPC11U6X_SYS_AHB_CLK_CTRL_USART3_4;
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}
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reset_mask = LPC11U6X_PRESET_CTRL_USART3;
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break;
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case LPC11U6X_CLOCK_USART4:
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if (!(--data->frg_in_use)) {
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deinit_frg = 1;
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}
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if (!(--data->usart34_in_use)) {
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clk_mask = LPC11U6X_SYS_AHB_CLK_CTRL_USART3_4;
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}
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reset_mask = LPC11U6X_PRESET_CTRL_USART4;
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break;
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default:
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k_mutex_unlock(&data->mutex);
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return -EINVAL;
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}
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syscon_ahb_clock_enable(cfg->syscon, clk_mask, false);
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if (deinit_frg) {
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syscon_frg_deinit(cfg->syscon);
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}
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syscon_peripheral_reset(cfg->syscon, reset_mask, true);
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k_mutex_unlock(&data->mutex);
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return ret;
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}
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static int lpc11u6x_clock_control_get_rate(const struct device *dev,
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clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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switch ((int) sub_system) {
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case LPC11U6X_CLOCK_I2C0:
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case LPC11U6X_CLOCK_I2C1:
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case LPC11U6X_CLOCK_GPIO:
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case LPC11U6X_CLOCK_USART0:
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*rate = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
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break;
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case LPC11U6X_CLOCK_USART1:
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case LPC11U6X_CLOCK_USART2:
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case LPC11U6X_CLOCK_USART3:
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case LPC11U6X_CLOCK_USART4:
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*rate = LPC11U6X_USART_CLOCK_RATE;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int lpc11u6x_syscon_init(const struct device *dev)
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{
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const struct lpc11u6x_syscon_config *cfg = dev->config;
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struct lpc11u6x_syscon_data *data = dev->data;
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uint32_t val;
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k_mutex_init(&data->mutex);
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data->frg_in_use = 0;
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data->usart34_in_use = 0;
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/* Enable SRAM1 and USB ram if needed */
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val = 0;
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#ifdef CONFIG_CLOCK_CONTROL_LPC11U6X_ENABLE_SRAM1
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val |= LPC11U6X_SYS_AHB_CLK_CTRL_SRAM1;
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#endif /* CONFIG_CLOCK_CONTROL_LPC11U6X_ENABLE_SRAM1 */
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#ifdef CONFIG_CLOCK_CONTROL_LPC11U6X_ENABLE_USB_RAM
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val |= LPC11U6X_SYS_AHB_CLK_CTRL_USB_SRAM;
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#endif /* CONFIG_CLOCK_CONTROL_LPC11U6X_ENABLE_USB_RAM */
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/* Enable IOCON (I/O Control) clock. */
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val |= LPC11U6X_SYS_AHB_CLK_CTRL_IOCON;
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syscon_ahb_clock_enable(cfg->syscon, val, true);
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/* Configure PLL output as the main clock source, with a frequency of
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* 48MHz
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*/
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#ifdef CONFIG_CLOCK_CONTROL_LPC11U6X_PLL_SRC_SYSOSC
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syscon_power_up(cfg->syscon, LPC11U6X_PDRUNCFG_SYSOSC_PD, true);
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/* Wait ~500us */
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for (int i = 0; i < 2500; i++) {
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}
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/* Configure PLL input */
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syscon_set_pll_src(cfg->syscon, LPC11U6X_SYS_PLL_CLK_SEL_SYSOSC);
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pinmux_enable_sysosc();
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#elif defined(CONFIG_CLOCK_CONTROL_LPC11U6X_PLL_SRC_IRC)
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syscon_power_up(cfg->syscon, LPC11U6X_PDRUNCFG_IRC_PD, true);
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syscon_set_pll_src(cfg->syscon, LPC11U6X_SYS_PLL_CLK_SEL_IRC);
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#endif
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/* Flash access takes 3 clock cycles for main clock frequencies
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* between 40MHz and 50MHz
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*/
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set_flash_access_time(LPC11U6X_FLASH_TIMING_3CYCLES);
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/* Shutdown PLL to change divider/mult ratios */
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syscon_power_up(cfg->syscon, LPC11U6X_PDRUNCFG_PLL_PD, false);
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/* Setup PLL to have 48MHz output */
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syscon_setup_pll(cfg->syscon, 3, 1);
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/* Power up pll and wait */
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syscon_power_up(cfg->syscon, LPC11U6X_PDRUNCFG_PLL_PD, true);
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while (!syscon_pll_locked(cfg->syscon)) {
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}
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cfg->syscon->sys_ahb_clk_div = 1;
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syscon_set_main_clock_source(cfg->syscon, LPC11U6X_MAIN_CLK_SRC_PLLOUT);
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return 0;
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}
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static const struct clock_control_driver_api lpc11u6x_clock_control_api = {
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.on = lpc11u6x_clock_control_on,
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.off = lpc11u6x_clock_control_off,
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.get_rate = lpc11u6x_clock_control_get_rate,
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};
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static const struct lpc11u6x_syscon_config syscon_config = {
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.syscon = (struct lpc11u6x_syscon_regs *) DT_INST_REG_ADDR(0),
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};
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static struct lpc11u6x_syscon_data syscon_data;
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DEVICE_DT_INST_DEFINE(0,
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&lpc11u6x_syscon_init,
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NULL,
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&syscon_data, &syscon_config,
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PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
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&lpc11u6x_clock_control_api);
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