360 lines
9.2 KiB
C
360 lines
9.2 KiB
C
/*
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* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <spi.h>
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#include <nrfx_spim.h>
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#include <string.h>
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#define LOG_DOMAIN "spi_nrfx_spim"
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#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(spi_nrfx_spim);
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#include "spi_context.h"
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struct spi_nrfx_data {
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struct spi_context ctx;
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size_t chunk_len;
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bool busy;
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#if (CONFIG_SPI_NRFX_RAM_BUFFER_SIZE > 0)
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u8_t buffer[CONFIG_SPI_NRFX_RAM_BUFFER_SIZE];
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#endif
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};
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struct spi_nrfx_config {
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nrfx_spim_t spim;
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size_t max_chunk_len;
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};
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static inline struct spi_nrfx_data *get_dev_data(struct device *dev)
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{
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return dev->driver_data;
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}
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static inline const struct spi_nrfx_config *get_dev_config(struct device *dev)
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{
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return dev->config->config_info;
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}
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static inline nrf_spim_frequency_t get_nrf_spim_frequency(u32_t frequency)
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{
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/* Get the highest supported frequency not exceeding the requested one.
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*/
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if (frequency < 250000) {
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return NRF_SPIM_FREQ_125K;
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} else if (frequency < 500000) {
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return NRF_SPIM_FREQ_250K;
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} else if (frequency < 1000000) {
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return NRF_SPIM_FREQ_500K;
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} else if (frequency < 2000000) {
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return NRF_SPIM_FREQ_1M;
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} else if (frequency < 4000000) {
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return NRF_SPIM_FREQ_2M;
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} else if (frequency < 8000000) {
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return NRF_SPIM_FREQ_4M;
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#ifdef CONFIG_SOC_NRF52840
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} else if (frequency < 16000000) {
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return NRF_SPIM_FREQ_8M;
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} else if (frequency < 32000000) {
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return NRF_SPIM_FREQ_16M;
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} else {
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return NRF_SPIM_FREQ_32M;
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#else
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} else {
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return NRF_SPIM_FREQ_8M;
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#endif
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}
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}
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static inline nrf_spim_mode_t get_nrf_spim_mode(u16_t operation)
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{
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if (SPI_MODE_GET(operation) & SPI_MODE_CPOL) {
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if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
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return NRF_SPIM_MODE_3;
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} else {
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return NRF_SPIM_MODE_2;
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}
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} else {
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if (SPI_MODE_GET(operation) & SPI_MODE_CPHA) {
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return NRF_SPIM_MODE_1;
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} else {
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return NRF_SPIM_MODE_0;
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}
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}
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}
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static inline nrf_spim_bit_order_t get_nrf_spim_bit_order(u16_t operation)
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{
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if (operation & SPI_TRANSFER_LSB) {
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return NRF_SPIM_BIT_ORDER_LSB_FIRST;
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} else {
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return NRF_SPIM_BIT_ORDER_MSB_FIRST;
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}
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}
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static int configure(struct device *dev,
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const struct spi_config *spi_cfg)
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{
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struct spi_context *ctx = &get_dev_data(dev)->ctx;
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const nrfx_spim_t *spim = &get_dev_config(dev)->spim;
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if (spi_context_configured(ctx, spi_cfg)) {
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/* Already configured. No need to do it again. */
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return 0;
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}
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if (SPI_OP_MODE_GET(spi_cfg->operation) != SPI_OP_MODE_MASTER) {
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LOG_ERR("Slave mode is not supported on %s",
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dev->config->name);
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return -EINVAL;
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}
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if (spi_cfg->operation & SPI_MODE_LOOP) {
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LOG_ERR("Loopback mode is not supported");
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return -EINVAL;
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}
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if ((spi_cfg->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
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LOG_ERR("Only single line mode is supported");
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return -EINVAL;
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}
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if (SPI_WORD_SIZE_GET(spi_cfg->operation) != 8) {
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LOG_ERR("Word sizes other than 8 bits"
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" are not supported");
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return -EINVAL;
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}
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if (spi_cfg->frequency < 125000) {
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LOG_ERR("Frequencies lower than 125 kHz are not supported");
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return -EINVAL;
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}
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ctx->config = spi_cfg;
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spi_context_cs_configure(ctx);
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nrf_spim_configure(spim->p_reg,
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get_nrf_spim_mode(spi_cfg->operation),
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get_nrf_spim_bit_order(spi_cfg->operation));
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nrf_spim_frequency_set(spim->p_reg,
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get_nrf_spim_frequency(spi_cfg->frequency));
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return 0;
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}
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static void transfer_next_chunk(struct device *dev)
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{
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struct spi_nrfx_data *dev_data = get_dev_data(dev);
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const struct spi_nrfx_config *dev_config = get_dev_config(dev);
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struct spi_context *ctx = &dev_data->ctx;
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int error = 0;
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size_t chunk_len = spi_context_longest_current_buf(ctx);
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if (chunk_len > 0) {
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nrfx_spim_xfer_desc_t xfer;
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nrfx_err_t result;
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const u8_t *tx_buf = ctx->tx_buf;
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#if (CONFIG_SPI_NRFX_RAM_BUFFER_SIZE > 0)
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if (spi_context_tx_buf_on(ctx) && !nrfx_is_in_ram(tx_buf)) {
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if (chunk_len > sizeof(dev_data->buffer)) {
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chunk_len = sizeof(dev_data->buffer);
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}
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memcpy(dev_data->buffer, tx_buf, chunk_len);
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tx_buf = dev_data->buffer;
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}
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#endif
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if (chunk_len > dev_config->max_chunk_len) {
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chunk_len = dev_config->max_chunk_len;
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}
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dev_data->chunk_len = chunk_len;
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xfer.p_tx_buffer = tx_buf;
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xfer.tx_length = spi_context_tx_buf_on(ctx) ? chunk_len : 0;
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xfer.p_rx_buffer = ctx->rx_buf;
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xfer.rx_length = spi_context_rx_buf_on(ctx) ? chunk_len : 0;
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result = nrfx_spim_xfer(&dev_config->spim, &xfer, 0);
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if (result == NRFX_SUCCESS) {
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return;
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}
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error = -EIO;
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}
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spi_context_cs_control(ctx, false);
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LOG_DBG("Transaction finished with status %d", error);
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spi_context_complete(ctx, error);
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dev_data->busy = false;
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}
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static int transceive(struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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struct spi_nrfx_data *dev_data = get_dev_data(dev);
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int error;
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error = configure(dev, spi_cfg);
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if (error == 0) {
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dev_data->busy = true;
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spi_context_buffers_setup(&dev_data->ctx, tx_bufs, rx_bufs, 1);
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spi_context_cs_control(&dev_data->ctx, true);
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transfer_next_chunk(dev);
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error = spi_context_wait_for_completion(&dev_data->ctx);
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}
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spi_context_release(&dev_data->ctx, error);
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return error;
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}
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static int spi_nrfx_transceive(struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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spi_context_lock(&get_dev_data(dev)->ctx, false, NULL);
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return transceive(dev, spi_cfg, tx_bufs, rx_bufs);
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}
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#ifdef CONFIG_SPI_ASYNC
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static int spi_nrfx_transceive_async(struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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struct k_poll_signal *async)
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{
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spi_context_lock(&get_dev_data(dev)->ctx, true, async);
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return transceive(dev, spi_cfg, tx_bufs, rx_bufs);
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}
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#endif /* CONFIG_SPI_ASYNC */
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static int spi_nrfx_release(struct device *dev,
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const struct spi_config *spi_cfg)
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{
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struct spi_nrfx_data *dev_data = get_dev_data(dev);
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if (!spi_context_configured(&dev_data->ctx, spi_cfg)) {
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return -EINVAL;
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}
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if (dev_data->busy) {
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return -EBUSY;
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}
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spi_context_unlock_unconditionally(&dev_data->ctx);
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return 0;
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}
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static const struct spi_driver_api spi_nrfx_driver_api = {
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.transceive = spi_nrfx_transceive,
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#ifdef CONFIG_SPI_ASYNC
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.transceive_async = spi_nrfx_transceive_async,
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#endif
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.release = spi_nrfx_release,
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};
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static void event_handler(const nrfx_spim_evt_t *p_event, void *p_context)
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{
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struct device *dev = p_context;
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struct spi_nrfx_data *dev_data = get_dev_data(dev);
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if (p_event->type == NRFX_SPIM_EVENT_DONE) {
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spi_context_update_tx(&dev_data->ctx, 1, dev_data->chunk_len);
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spi_context_update_rx(&dev_data->ctx, 1, dev_data->chunk_len);
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transfer_next_chunk(dev);
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}
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}
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static int init_spim(struct device *dev, const nrfx_spim_config_t *config)
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{
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/* This sets only default values of frequency, mode and bit order.
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* The proper ones are set in configure() when a transfer is started.
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*/
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nrfx_err_t result = nrfx_spim_init(&get_dev_config(dev)->spim,
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config,
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event_handler,
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dev);
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if (result != NRFX_SUCCESS) {
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LOG_ERR("Failed to initialize device: %s",
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dev->config->name);
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return -EBUSY;
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}
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spi_context_unlock_unconditionally(&get_dev_data(dev)->ctx);
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return 0;
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}
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#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
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#define SPI_NRFX_SPIM_EXTENDED_CONFIG(idx) \
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.rx_delay = CONFIG_SPI_##idx##_NRF_RX_DELAY,
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#else
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#define SPI_NRFX_SPIM_EXTENDED_CONFIG(idx)
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#endif
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#define SPI_NRFX_SPIM_DEVICE(idx) \
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static int spi_##idx##_init(struct device *dev) \
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{ \
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IRQ_CONNECT(NRFX_IRQ_NUMBER_GET(NRF_SPIM##idx), \
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CONFIG_SPI_##idx##_IRQ_PRI, \
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nrfx_isr, nrfx_spim_##idx##_irq_handler, 0); \
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const nrfx_spim_config_t config = { \
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.sck_pin = DT_SPI_##idx##_NRF_SCK_PIN, \
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.mosi_pin = DT_SPI_##idx##_NRF_MOSI_PIN, \
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.miso_pin = DT_SPI_##idx##_NRF_MISO_PIN, \
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.ss_pin = NRFX_SPIM_PIN_NOT_USED, \
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.orc = CONFIG_SPI_##idx##_NRF_ORC, \
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.frequency = NRF_SPIM_FREQ_4M, \
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.mode = NRF_SPIM_MODE_0, \
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.bit_order = NRF_SPIM_BIT_ORDER_MSB_FIRST, \
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SPI_NRFX_SPIM_EXTENDED_CONFIG(idx) \
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}; \
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return init_spim(dev, &config); \
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} \
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static struct spi_nrfx_data spi_##idx##_data = { \
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SPI_CONTEXT_INIT_LOCK(spi_##idx##_data, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_##idx##_data, ctx), \
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.busy = false, \
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}; \
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static const struct spi_nrfx_config spi_##idx##_config = { \
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.spim = NRFX_SPIM_INSTANCE(idx), \
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.max_chunk_len = (1 << SPIM##idx##_EASYDMA_MAXCNT_SIZE) - 1, \
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}; \
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DEVICE_AND_API_INIT(spi_##idx, CONFIG_SPI_##idx##_NAME, \
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spi_##idx##_init, \
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&spi_##idx##_data, \
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&spi_##idx##_config, \
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POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
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&spi_nrfx_driver_api)
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#ifdef CONFIG_SPI_0_NRF_SPIM
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SPI_NRFX_SPIM_DEVICE(0);
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#endif
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#ifdef CONFIG_SPI_1_NRF_SPIM
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SPI_NRFX_SPIM_DEVICE(1);
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#endif
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#ifdef CONFIG_SPI_2_NRF_SPIM
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SPI_NRFX_SPIM_DEVICE(2);
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#endif
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#ifdef CONFIG_SPI_3_NRF_SPIM
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SPI_NRFX_SPIM_DEVICE(3);
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#endif
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