81 lines
1.9 KiB
C
81 lines
1.9 KiB
C
/*
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* Copyright (c) 2023 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_USB_DEVICE_USB_DC_DW_STM32_H
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#define ZEPHYR_DRIVERS_USB_DEVICE_USB_DC_DW_STM32_H
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#include <stdint.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include "usb_dw_registers.h"
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struct usb_dw_stm32_clk {
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const struct device *const dev;
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const struct stm32_pclken *const pclken;
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size_t pclken_len;
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};
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static inline int clk_enable_st_stm32f4_fsotg(const struct usb_dw_stm32_clk *const clk)
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{
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int ret;
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if (!device_is_ready(clk->dev)) {
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return -ENODEV;
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}
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if (clk->pclken_len > 1) {
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uint32_t clk_rate;
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ret = clock_control_configure(clk->dev,
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(void *)&clk->pclken[1],
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NULL);
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if (ret) {
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return ret;
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}
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ret = clock_control_get_rate(clk->dev,
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(void *)&clk->pclken[1],
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&clk_rate);
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if (ret) {
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return ret;
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}
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if (clk_rate != MHZ(48)) {
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return -ENOTSUP;
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}
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}
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return clock_control_on(clk->dev, (void *)&clk->pclken[0]);
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}
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static inline int pwr_on_st_stm32f4_fsotg(struct usb_dw_reg *const base)
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{
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base->ggpio |= USB_DW_GGPIO_STM32_PWRDWN | USB_DW_GGPIO_STM32_VBDEN;
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return 0;
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}
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#define QUIRK_ST_STM32F4_FSOTG_DEFINE(n) \
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static const struct stm32_pclken pclken_##n[] = STM32_DT_INST_CLOCKS(n);\
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\
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static const struct usb_dw_stm32_clk stm32f4_clk_##n = { \
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.dev = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), \
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.pclken = pclken_##n, \
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.pclken_len = DT_INST_NUM_CLOCKS(n), \
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}; \
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\
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static int clk_enable_st_stm32f4_fsotg_##n(void) \
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{ \
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return clk_enable_st_stm32f4_fsotg(&stm32f4_clk_##n); \
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}
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#define USB_DW_QUIRK_ST_STM32F4_FSOTG_DEFINE(n) \
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COND_CODE_1(DT_NODE_HAS_COMPAT(DT_DRV_INST(n), st_stm32f4_fsotg), \
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(QUIRK_ST_STM32F4_FSOTG_DEFINE(n)), ())
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#endif /* ZEPHYR_DRIVERS_USB_DEVICE_USB_DC_DW_STM32_H */
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