325 lines
10 KiB
C
325 lines
10 KiB
C
/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include <fsl_iomuxc.h>
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#include <fsl_gpio.h>
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#include <soc.h>
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#ifdef CONFIG_ETH_MCUX_0
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static gpio_pin_config_t enet_gpio_config = {
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.direction = kGPIO_DigitalOutput,
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.outputLogic = 0,
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.interruptMode = kGPIO_NoIntmode
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};
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#endif
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#ifdef CONFIG_DISK_ACCESS_USDHC1
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/*Drive Strength Field: R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
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*Speed Field: medium(100MHz)
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*Open Drain Enable Field: Open Drain Disabled
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*Pull / Keep Enable Field: Pull/Keeper Enabled
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*Pull / Keep Select Field: Pull
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*Pull Up / Down Config. Field: 47K Ohm Pull Up
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*Hyst. Enable Field: Hysteresis Enabled.
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*/
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static void mimxrt1050_evk_usdhc_pinmux(
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u16_t nusdhc, bool init,
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u32_t speed, u32_t strength)
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{
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u32_t cmd_data = IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) |
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IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength);
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u32_t clk = IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) |
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IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(strength);
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if (nusdhc == 0) {
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if (init) {
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B0_05_GPIO1_IO05,
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0U);
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IOMUXC_SetPinMux(/*SD_CD*/
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IOMUXC_GPIO_B1_12_GPIO2_IO28,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_14_USDHC1_VSELECT,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
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0U);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_05_GPIO1_IO05,
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0x10B0u);
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IOMUXC_SetPinConfig(/*SD0_CD_SW*/
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IOMUXC_GPIO_B1_12_GPIO2_IO28,
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0x017089u);
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IOMUXC_SetPinConfig(/*SD0_VSELECT*/
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IOMUXC_GPIO_B1_14_USDHC1_VSELECT,
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0x0170A1u);
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}
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
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cmd_data);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
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clk);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
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cmd_data);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
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cmd_data);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
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cmd_data);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
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cmd_data);
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}
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}
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#endif
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static int mimxrt1050_evk_init(struct device *dev)
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{
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ARG_UNUSED(dev);
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
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#ifndef CONFIG_ETH_MCUX_0
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/* LED */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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/* SW0 */
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IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0);
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#endif
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#ifdef CONFIG_UART_MCUX_LPUART_1
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/* LPUART1 TX/RX */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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#ifdef CONFIG_UART_MCUX_LPUART_3
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/* LPUART3 TX/RX */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPUART3_RX, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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#ifdef CONFIG_I2C_1
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/* LPI2C1 SCL, SDA */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 1);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 1);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL,
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IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA,
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IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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#ifdef CONFIG_SPI_3
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/* LPSPI3 SCK, SDO, SDI, PCS0 */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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#ifdef CONFIG_ETH_MCUX_0
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0xB0A9u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0xB0A9u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 0x31);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDC, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0xB829);
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IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
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/* Intialize ENET_INT GPIO */
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GPIO_PinInit(GPIO1, 9, &enet_gpio_config);
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GPIO_PinInit(GPIO1, 10, &enet_gpio_config);
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/* pull up the ENET_INT before RESET. */
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GPIO_WritePinOutput(GPIO1, 10, 1);
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GPIO_WritePinOutput(GPIO1, 9, 0);
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#endif
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#ifdef CONFIG_DISPLAY_MCUX_ELCDIF
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IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_00_LCD_CLK, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_04_LCD_DATA00, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_05_LCD_DATA01, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_06_LCD_DATA02, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_07_LCD_DATA03, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_08_LCD_DATA04, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_09_LCD_DATA05, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_10_LCD_DATA06, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_11_LCD_DATA07, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_12_LCD_DATA08, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_13_LCD_DATA09, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_14_LCD_DATA10, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_15_LCD_DATA11, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_LCD_DATA12, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_LCD_DATA13, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_02_LCD_DATA14, 0x01B0B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_03_LCD_DATA15, 0x01B0B0u);
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/* LCD Reset */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0x10B0u);
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/* LCD Backlight */
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x10B0u);
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gpio_pin_config_t config = {
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kGPIO_DigitalOutput, 0,
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};
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config.outputLogic = 1;
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GPIO_PinInit(GPIO2, 31, &config);
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#endif
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#ifdef CONFIG_DISK_ACCESS_USDHC1
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mimxrt1050_evk_usdhc_pinmux(0, true, 2, 1);
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imxrt_usdhc_pinmux_cb_register(mimxrt1050_evk_usdhc_pinmux);
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#endif
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return 0;
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}
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#ifdef CONFIG_ETH_MCUX_0
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static int mimxrt1050_evk_phy_reset(struct device *dev)
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{
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/* RESET PHY chip. */
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k_busy_wait(USEC_PER_MSEC * 10U);
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GPIO_WritePinOutput(GPIO1, 9, 1);
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return 0;
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}
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#endif
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SYS_INIT(mimxrt1050_evk_init, PRE_KERNEL_1, 0);
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#ifdef CONFIG_ETH_MCUX_0
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SYS_INIT(mimxrt1050_evk_phy_reset, PRE_KERNEL_2, 0);
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#endif
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