19 lines
406 B
C
19 lines
406 B
C
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __COMMON_ADSP_CACHE_H__
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#define __COMMON_ADSP_CACHE_H__
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#include <xtensa/hal.h>
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/* macros for data cache operations */
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#define SOC_DCACHE_FLUSH(addr, size) \
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xthal_dcache_region_writeback((addr), (size))
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#define SOC_DCACHE_INVALIDATE(addr, size) \
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xthal_dcache_region_invalidate((addr), (size))
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#endif
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