zephyr/soc/xtensa/intel_adsp/cavs_v15
Andy Ross e6dfae0fea soc/intel_adsp: Fix linker warning
The linker will emit a warning condition when a section with a
declared alignment doesn't naturally start on that alignment (which
begets the question of why the declared alignment syntax exists at
all...).

Do the alignment for .bss between the sections instead as a simple
workaround.

Note that this alignment isn't architecturally required, as current
Zephyr targets don't use the page-aligned pseudo-MMU on this hardware;
the only requirement is alignment to the 64 byte cache stride.  It
should work to pack .bss tightly.  But when I try that, I get an error
from the rimage tool, which is apparently unprepared for
non-4k-aligned sections?

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-10-21 06:38:53 -04:00
..
include soc/xtensa: Misc. checkpatch fixups 2020-10-21 06:38:53 -04:00
Kconfig.defconfig.series soc/xtensa: Misc. checkpatch fixups 2020-10-21 06:38:53 -04:00
Kconfig.series
Kconfig.soc
linker.ld soc/intel_adsp: Fix linker warning 2020-10-21 06:38:53 -04:00