110 lines
2.7 KiB
C
110 lines
2.7 KiB
C
/*
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT espressif_esp32_rtc
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#include <zephyr/dt-bindings/clock/esp32c3_clock.h>
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#include <hal/clk_gate_ll.h>
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#include <soc/soc_caps.h>
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#include <soc/soc.h>
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#include <soc/rtc.h>
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#include <rtc_clk_common.h>
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#include <soc.h>
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#include <zephyr/drivers/clock_control.h>
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#include <driver/periph_ctrl.h>
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static int clock_control_esp32_on(const struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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periph_module_enable((periph_module_t)sys);
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return 0;
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}
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static int clock_control_esp32_off(const struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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periph_module_disable((periph_module_t)sys);
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return 0;
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}
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static enum clock_control_status clock_control_esp32_get_status(const struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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uint32_t clk_en_reg = periph_ll_get_clk_en_reg((periph_module_t)sys);
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uint32_t clk_en_mask = periph_ll_get_clk_en_mask((periph_module_t)sys);
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if (DPORT_GET_PERI_REG_MASK(clk_en_reg, clk_en_mask)) {
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return CLOCK_CONTROL_STATUS_ON;
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}
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return CLOCK_CONTROL_STATUS_OFF;
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}
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static int clock_control_esp32_get_rate(const struct device *dev,
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clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(sub_system);
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uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL);
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uint32_t cpuperiod_sel;
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uint32_t source_freq_mhz;
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uint32_t clk_div;
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switch (soc_clk_sel) {
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case DPORT_SOC_CLK_SEL_XTAL:
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clk_div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1;
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source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get();
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*rate = MHZ(source_freq_mhz / clk_div);
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return 0;
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case DPORT_SOC_CLK_SEL_PLL:
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cpuperiod_sel = DPORT_REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL);
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if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) {
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*rate = MHZ(80);
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} else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) {
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*rate = MHZ(160);
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} else {
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*rate = 0;
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return -ENOTSUP;
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}
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return 0;
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case DPORT_SOC_CLK_SEL_8M:
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*rate = MHZ(8);
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return 0;
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default:
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*rate = 0;
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return -ENOTSUP;
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}
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}
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static int clock_control_esp32_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return 0;
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}
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static const struct clock_control_driver_api clock_control_esp32_api = {
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.on = clock_control_esp32_on,
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.off = clock_control_esp32_off,
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.async_on = NULL,
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.get_rate = clock_control_esp32_get_rate,
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.get_status = clock_control_esp32_get_status,
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};
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DEVICE_DT_DEFINE(DT_NODELABEL(rtc),
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&clock_control_esp32_init,
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NULL,
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NULL,
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NULL,
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PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
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&clock_control_esp32_api);
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