55 lines
904 B
Plaintext
55 lines
904 B
Plaintext
#include <arm/armv7-m.dtsi>
|
|
|
|
/ {
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-m3";
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
sram0: memory@20000000 {
|
|
device_type = "memory";
|
|
compatible = "mmio-sram";
|
|
reg = <0x20000000 (64*1024)>;
|
|
};
|
|
|
|
flash0: flash@0 {
|
|
reg = <0x00000000 (256*1024)>;
|
|
};
|
|
|
|
soc {
|
|
uart0: uart@4000C000 {
|
|
compatible = "ti,stellaris-uart";
|
|
reg = <0x4000C000 0x4c>;
|
|
interrupts = <5 3>;
|
|
status = "disabled";
|
|
label = "UART_0";
|
|
};
|
|
|
|
uart1: uart@4000D000 {
|
|
compatible = "ti,stellaris-uart";
|
|
reg = <0x4000D000 0x4c>;
|
|
interrupts = <6 3>;
|
|
status = "disabled";
|
|
label = "UART_1";
|
|
};
|
|
|
|
uart2: uart@4000E000 {
|
|
compatible = "ti,stellaris-uart";
|
|
reg = <0x4000E000 0x4c>;
|
|
interrupts = <33 3>;
|
|
status = "disabled";
|
|
label = "UART_2";
|
|
};
|
|
};
|
|
};
|
|
|
|
&nvic {
|
|
arm,num-irq-priority-bits = <3>;
|
|
};
|