157 lines
4.1 KiB
C
157 lines
4.1 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2021 Linaro Limited
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* Copyright (c) 2021 Nordic Semiconductor ASA
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* Copyright (c) 2021 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_xec_pinctrl
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#include <zephyr/drivers/pinctrl.h>
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#include <soc.h>
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/* Microchip XEC: each GPIO pin has two 32-bit control register.
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* The first 32-bit register contains all pin features except
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* slew rate and driver strength in the second control register.
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* We compute the register index from the beginning of the GPIO
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* control address space which is the same range of the PINCTRL
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* parent node.
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*/
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static void config_drive_slew(struct gpio_regs * const regs, uint32_t idx, uint32_t conf)
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{
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uint32_t slew = conf & (MCHP_XEC_OSPEEDR_MASK << MCHP_XEC_OSPEEDR_POS);
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uint32_t drvstr = conf & (MCHP_XEC_ODRVSTR_MASK << MCHP_XEC_ODRVSTR_POS);
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uint32_t val = 0;
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uint32_t mask = 0;
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if (slew != MCHP_XEC_OSPEEDR_NO_CHG) {
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mask |= MCHP_GPIO_CTRL2_SLEW_MASK;
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if (slew == MCHP_XEC_OSPEEDR_FAST) {
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val |= MCHP_GPIO_CTRL2_SLEW_FAST;
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}
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}
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if (drvstr != MCHP_XEC_ODRVSTR_NO_CHG) {
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mask |= MCHP_GPIO_CTRL2_DRV_STR_MASK;
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val |= (drvstr << MCHP_GPIO_CTRL2_DRV_STR_POS);
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}
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if (!mask) {
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return;
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}
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regs->CTRL2[idx] = (regs->CTRL2[idx] & ~mask) | (val & mask);
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}
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/* Configure pin by writing GPIO Control and Control2 registers.
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* NOTE: Disable alternate output feature since the GPIO driver does.
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* While alternate output is enabled (default state of pin) HW does not
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* ignores writes to the parallel output bit for the pin. To set parallel
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* output value we must keep pin direction as input, set alternate output
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* disable, program pin value to parallel output bit, and then disable
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* alternate output mode.
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*/
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static int xec_config_pin(uint32_t portpin, uint32_t conf, uint32_t altf)
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{
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struct gpio_regs * const regs = (struct gpio_regs * const)DT_INST_REG_ADDR(0);
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uint32_t port = MCHP_XEC_PINMUX_PORT(portpin);
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uint32_t pin = (uint32_t)MCHP_XEC_PINMUX_PIN(portpin);
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uint32_t msk = MCHP_GPIO_CTRL_AOD_MASK;
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uint32_t val = MCHP_GPIO_CTRL_AOD_DIS;
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uint32_t idx = 0u;
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uint32_t temp = 0u;
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if (port >= NUM_MCHP_GPIO_PORTS) {
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return -EINVAL;
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}
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/* MCHP XEC family is 32 pins per port */
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idx = (port * 32U) + pin;
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config_drive_slew(regs, idx, conf);
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/* default input pad enabled, buffer type push-pull, no internal pulls,
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* and invert polarity normal.
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*/
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msk |= (BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS) | MCHP_GPIO_CTRL_BUFT_MASK |
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MCHP_GPIO_CTRL_PUD_MASK | MCHP_GPIO_CTRL_MUX_MASK
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| BIT(MCHP_GPIO_CTRL_POL_POS));
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if (conf & BIT(MCHP_XEC_PIN_LOW_POWER_POS)) {
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msk |= MCHP_GPIO_CTRL_PWRG_MASK;
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val |= MCHP_GPIO_CTRL_PWRG_OFF;
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}
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temp = (conf & MCHP_XEC_PUPDR_MASK) >> MCHP_XEC_PUPDR_POS;
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switch (temp) {
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case MCHP_XEC_PULL_UP:
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val |= MCHP_GPIO_CTRL_PUD_PU;
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break;
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case MCHP_XEC_PULL_DOWN:
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val |= MCHP_GPIO_CTRL_PUD_PD;
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break;
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case MCHP_XEC_REPEATER:
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val |= MCHP_GPIO_CTRL_PUD_RPT;
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break;
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default:
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val |= MCHP_GPIO_CTRL_PUD_NONE;
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break;
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}
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if ((conf >> MCHP_XEC_OTYPER_POS) & MCHP_XEC_OTYPER_MASK) {
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val |= MCHP_GPIO_CTRL_BUFT_OPENDRAIN;
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}
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if (conf & MCHP_XEC_FUNC_INV_MSK) {
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val |= BIT(MCHP_GPIO_CTRL_POL_POS);
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}
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regs->CTRL[idx] = (regs->CTRL[idx] & ~msk) | val;
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temp = (conf >> MCHP_XEC_OVAL_POS) & MCHP_XEC_OVAL_MASK;
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if (temp) {
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if (temp == MCHP_XEC_OVAL_DRV_HIGH) {
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regs->PAROUT[port] |= BIT(pin);
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} else {
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regs->PAROUT[port] &= ~BIT(pin);
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}
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regs->CTRL[idx] |= MCHP_GPIO_CTRL_DIR_OUTPUT;
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}
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val = (uint32_t)((altf & MCHP_GPIO_CTRL_MUX_MASK0) << MCHP_GPIO_CTRL_MUX_POS);
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regs->CTRL[idx] |= val;
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return 0;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
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uint32_t portpin, mux, cfg, func;
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int ret;
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ARG_UNUSED(reg);
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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mux = pins[i].pinmux;
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func = MCHP_XEC_PINMUX_FUNC(mux);
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if (func >= MCHP_AFMAX) {
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return -EINVAL;
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}
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cfg = pins[i].pincfg;
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portpin = MEC_XEC_PINMUX_PORT_PIN(mux);
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ret = xec_config_pin(portpin, cfg, func);
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if (ret < 0) {
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return ret;
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}
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}
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return 0;
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}
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