173 lines
3.5 KiB
C
173 lines
3.5 KiB
C
/*
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* Copyright (c) 2018 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief x86 specific sycall header
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*
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* This header contains the x86 specific sycall interface. It is
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* included by the syscall interface architecture-abstraction header
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* (include/arch/syscall.h)
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_X86_SYSCALL_H_
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#define ZEPHYR_INCLUDE_ARCH_X86_SYSCALL_H_
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#define USER_CODE_SEG 0x2b /* at dpl=3 */
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#define USER_DATA_SEG 0x33 /* at dpl=3 */
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#ifdef CONFIG_USERSPACE
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#ifndef _ASMLANGUAGE
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#include <zephyr/types.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Syscall invocation macros. x86-specific machine constraints used to ensure
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* args land in the proper registers, see implementation of
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* _x86_syscall_entry_stub in userspace.S
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*
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* the entry stub clobbers EDX and ECX on IAMCU systems
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*/
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static inline u32_t _arch_syscall_invoke6(u32_t arg1, u32_t arg2, u32_t arg3,
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u32_t arg4, u32_t arg5, u32_t arg6,
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u32_t call_id)
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{
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u32_t ret;
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__asm__ volatile("push %%ebp\n\t"
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"mov %[arg6], %%ebp\n\t"
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"int $0x80\n\t"
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"pop %%ebp\n\t"
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: "=a" (ret)
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#ifdef CONFIG_X86_IAMCU
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, "=d" (arg2), "=c" (arg3)
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#endif
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: "S" (call_id), "a" (arg1), "d" (arg2),
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"c" (arg3), "b" (arg4), "D" (arg5),
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[arg6] "m" (arg6)
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: "memory", "esp");
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return ret;
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}
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static inline u32_t _arch_syscall_invoke5(u32_t arg1, u32_t arg2, u32_t arg3,
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u32_t arg4, u32_t arg5, u32_t call_id)
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{
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u32_t ret;
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__asm__ volatile("int $0x80"
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: "=a" (ret)
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#ifdef CONFIG_X86_IAMCU
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, "=d" (arg2), "=c" (arg3)
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#endif
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: "S" (call_id), "a" (arg1), "d" (arg2),
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"c" (arg3), "b" (arg4), "D" (arg5)
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: "memory");
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return ret;
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}
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static inline u32_t _arch_syscall_invoke4(u32_t arg1, u32_t arg2, u32_t arg3,
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u32_t arg4, u32_t call_id)
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{
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u32_t ret;
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__asm__ volatile("int $0x80"
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: "=a" (ret)
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#ifdef CONFIG_X86_IAMCU
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, "=d" (arg2), "=c" (arg3)
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#endif
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: "S" (call_id), "a" (arg1), "d" (arg2), "c" (arg3),
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"b" (arg4)
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: "memory");
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return ret;
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}
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static inline u32_t _arch_syscall_invoke3(u32_t arg1, u32_t arg2, u32_t arg3,
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u32_t call_id)
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{
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u32_t ret;
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__asm__ volatile("int $0x80"
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: "=a" (ret)
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#ifdef CONFIG_X86_IAMCU
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, "=d" (arg2), "=c" (arg3)
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#endif
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: "S" (call_id), "a" (arg1), "d" (arg2), "c" (arg3)
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: "memory");
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return ret;
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}
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static inline u32_t _arch_syscall_invoke2(u32_t arg1, u32_t arg2, u32_t call_id)
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{
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u32_t ret;
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__asm__ volatile("int $0x80"
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: "=a" (ret)
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#ifdef CONFIG_X86_IAMCU
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, "=d" (arg2)
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#endif
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: "S" (call_id), "a" (arg1), "d" (arg2)
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: "memory"
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#ifdef CONFIG_X86_IAMCU
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, "ecx"
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#endif
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);
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return ret;
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}
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static inline u32_t _arch_syscall_invoke1(u32_t arg1, u32_t call_id)
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{
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u32_t ret;
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__asm__ volatile("int $0x80"
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: "=a" (ret)
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: "S" (call_id), "a" (arg1)
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: "memory"
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#ifdef CONFIG_X86_IAMCU
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, "edx", "ecx"
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#endif
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);
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return ret;
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}
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static inline u32_t _arch_syscall_invoke0(u32_t call_id)
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{
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u32_t ret;
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__asm__ volatile("int $0x80"
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: "=a" (ret)
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: "S" (call_id)
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: "memory"
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#ifdef CONFIG_X86_IAMCU
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, "edx", "ecx"
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#endif
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);
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return ret;
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}
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static inline bool _arch_is_user_context(void)
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{
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int cs;
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/* On x86, read the CS register (which cannot be manually set) */
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__asm__ volatile ("mov %%cs, %[cs_val]" : [cs_val] "=r" (cs));
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return cs == USER_CODE_SEG;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* CONFIG_USERSPACE */
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#endif /* ZEPHYR_INCLUDE_ARCH_X86_SYSCALL_H_ */
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