240 lines
6.4 KiB
C
240 lines
6.4 KiB
C
/*
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* Copyright (c) 2016 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <counter.h>
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#include <device.h>
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#include <errno.h>
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#include <init.h>
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#include <soc.h>
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#include <clock_control/arm_clock_control.h>
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#include "timer_cmsdk_apb.h"
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typedef void (*timer_config_func_t)(struct device *dev);
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struct tmr_cmsdk_apb_cfg {
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struct counter_config_info info;
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volatile struct timer_cmsdk_apb *timer;
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timer_config_func_t timer_config_func;
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/* Timer Clock control in Active State */
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const struct arm_clock_control_t timer_cc_as;
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/* Timer Clock control in Sleep State */
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const struct arm_clock_control_t timer_cc_ss;
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/* Timer Clock control in Deep Sleep State */
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const struct arm_clock_control_t timer_cc_dss;
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};
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struct tmr_cmsdk_apb_dev_data {
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counter_top_callback_t top_callback;
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void *top_user_data;
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u32_t load;
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};
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static int tmr_cmsdk_apb_start(struct device *dev)
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{
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const struct tmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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struct tmr_cmsdk_apb_dev_data *data = dev->driver_data;
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/* Set the timer reload to count */
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cfg->timer->reload = data->load;
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cfg->timer->ctrl = TIMER_CTRL_EN;
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return 0;
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}
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static int tmr_cmsdk_apb_stop(struct device *dev)
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{
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const struct tmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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/* Disable the timer */
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cfg->timer->ctrl = 0x0;
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return 0;
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}
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static u32_t tmr_cmsdk_apb_read(struct device *dev)
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{
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const struct tmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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struct tmr_cmsdk_apb_dev_data *data = dev->driver_data;
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/* Return Counter Value */
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return data->load - cfg->timer->value;
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}
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static int tmr_cmsdk_apb_set_top_value(struct device *dev,
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u32_t ticks,
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counter_top_callback_t callback,
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void *user_data)
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{
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const struct tmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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struct tmr_cmsdk_apb_dev_data *data = dev->driver_data;
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data->top_callback = callback;
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data->top_user_data = user_data;
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/* Store the reload value */
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data->load = ticks;
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/* Set value register to count */
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cfg->timer->value = ticks;
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/* Set the timer reload to count */
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cfg->timer->reload = ticks;
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/* Enable IRQ */
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cfg->timer->ctrl |= TIMER_CTRL_IRQ_EN;
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return 0;
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}
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static u32_t tmr_cmsdk_apb_get_top_value(struct device *dev)
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{
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struct tmr_cmsdk_apb_dev_data *data = dev->driver_data;
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u32_t ticks = data->load;
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return ticks;
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}
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static u32_t tmr_cmsdk_apb_get_pending_int(struct device *dev)
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{
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const struct tmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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return cfg->timer->intstatus;
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}
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static const struct counter_driver_api tmr_cmsdk_apb_api = {
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.start = tmr_cmsdk_apb_start,
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.stop = tmr_cmsdk_apb_stop,
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.read = tmr_cmsdk_apb_read,
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.set_top_value = tmr_cmsdk_apb_set_top_value,
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.get_pending_int = tmr_cmsdk_apb_get_pending_int,
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.get_top_value = tmr_cmsdk_apb_get_top_value,
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};
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static void tmr_cmsdk_apb_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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struct tmr_cmsdk_apb_dev_data *data = dev->driver_data;
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const struct tmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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cfg->timer->intclear = TIMER_CTRL_INT_CLEAR;
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if (data->top_callback) {
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data->top_callback(dev, data->top_user_data);
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}
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}
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static int tmr_cmsdk_apb_init(struct device *dev)
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{
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const struct tmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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#ifdef CONFIG_CLOCK_CONTROL
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/* Enable clock for subsystem */
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struct device *clk =
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device_get_binding(CONFIG_ARM_CLOCK_CONTROL_DEV_NAME);
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#ifdef CONFIG_SOC_SERIES_BEETLE
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clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_as);
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clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_ss);
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clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_dss);
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#endif /* CONFIG_SOC_SERIES_BEETLE */
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#endif /* CONFIG_CLOCK_CONTROL */
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cfg->timer_config_func(dev);
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return 0;
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}
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/* TIMER 0 */
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#ifdef DT_ARM_CMSDK_TIMER_0
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static void timer_cmsdk_apb_config_0(struct device *dev);
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static const struct tmr_cmsdk_apb_cfg tmr_cmsdk_apb_cfg_0 = {
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.info = {
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.max_top_value = UINT32_MAX,
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.freq = 24000000U,
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.count_up = false,
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.channels = 0U,
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},
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.timer = ((volatile struct timer_cmsdk_apb *)DT_ARM_CMSDK_TIMER_0_BASE_ADDRESS),
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.timer_config_func = timer_cmsdk_apb_config_0,
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.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
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.device = DT_ARM_CMSDK_TIMER_0_BASE_ADDRESS,},
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.timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
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.device = DT_ARM_CMSDK_TIMER_0_BASE_ADDRESS,},
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.timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
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.device = DT_ARM_CMSDK_TIMER_0_BASE_ADDRESS,},
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};
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static struct tmr_cmsdk_apb_dev_data tmr_cmsdk_apb_dev_data_0 = {
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.load = UINT32_MAX,
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};
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DEVICE_AND_API_INIT(tmr_cmsdk_apb_0,
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DT_ARM_CMSDK_TIMER_0_LABEL,
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tmr_cmsdk_apb_init, &tmr_cmsdk_apb_dev_data_0,
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&tmr_cmsdk_apb_cfg_0, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&tmr_cmsdk_apb_api);
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static void timer_cmsdk_apb_config_0(struct device *dev)
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{
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IRQ_CONNECT(DT_ARM_CMSDK_TIMER_0_IRQ_0, DT_ARM_CMSDK_TIMER_0_IRQ_0_PRIORITY,
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tmr_cmsdk_apb_isr,
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DEVICE_GET(tmr_cmsdk_apb_0), 0);
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irq_enable(DT_ARM_CMSDK_TIMER_0_IRQ_0);
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}
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#endif /* DT_ARM_CMSDK_TIMER_0 */
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/* TIMER 1 */
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#ifdef DT_ARM_CMSDK_TIMER_1
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static void timer_cmsdk_apb_config_1(struct device *dev);
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static const struct tmr_cmsdk_apb_cfg tmr_cmsdk_apb_cfg_1 = {
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.info = {
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.max_top_value = UINT32_MAX,
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.freq = 24000000U,
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.count_up = false,
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.channels = 0U,
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},
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.timer = ((volatile struct timer_cmsdk_apb *)DT_ARM_CMSDK_TIMER_1_BASE_ADDRESS),
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.timer_config_func = timer_cmsdk_apb_config_1,
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.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
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.device = DT_ARM_CMSDK_TIMER_1_BASE_ADDRESS,},
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.timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
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.device = DT_ARM_CMSDK_TIMER_1_BASE_ADDRESS,},
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.timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
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.device = DT_ARM_CMSDK_TIMER_1_BASE_ADDRESS,},
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};
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static struct tmr_cmsdk_apb_dev_data tmr_cmsdk_apb_dev_data_1 = {
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.load = UINT32_MAX,
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};
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DEVICE_AND_API_INIT(tmr_cmsdk_apb_1,
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DT_ARM_CMSDK_TIMER_1_LABEL,
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tmr_cmsdk_apb_init, &tmr_cmsdk_apb_dev_data_1,
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&tmr_cmsdk_apb_cfg_1, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&tmr_cmsdk_apb_api);
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static void timer_cmsdk_apb_config_1(struct device *dev)
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{
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IRQ_CONNECT(DT_ARM_CMSDK_TIMER_1_IRQ_0, DT_ARM_CMSDK_TIMER_1_IRQ_0_PRIORITY,
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tmr_cmsdk_apb_isr,
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DEVICE_GET(tmr_cmsdk_apb_1), 0);
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irq_enable(DT_ARM_CMSDK_TIMER_1_IRQ_0);
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}
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#endif /* DT_ARM_CMSDK_TIMER_1 */
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