77 lines
1.5 KiB
YAML
77 lines
1.5 KiB
YAML
description: Xilinx AXI GPIO IP node
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compatible: "xlnx,xps-gpio-1.00.a"
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include: [gpio-controller.yaml, base.yaml]
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bus: xlnx,xps-gpio-1.00.a
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# Property names correspond to a subset of those generated by
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# https://github.com/Xilinx/device-tree-xlnx
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properties:
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reg:
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required: true
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xlnx,all-inputs:
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type: int
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description: |
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1 if all GPIOs are inputs, 0 otherwise
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xlnx,all-outputs:
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type: int
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description: |
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1 if all GPIOs are outputs, 0 otherwise
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xlnx,dout-default:
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type: int
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description: |
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Default output value. If n-th bit is 1, GPIO-n default value is 1.
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xlnx,gpio-width:
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type: int
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description: |
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Number of GPIOs supported
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xlnx,tri-default:
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type: int
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description: |
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Default tristate register value. If n-th bit is 1, GPIO-n is an input.
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xlnx,is-dual:
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type: int
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description: |
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1 if controller has GPIO2 enabled, 0 otherwise
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xlnx,all-inputs-2:
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type: int
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description: |
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1 if all GPIO2s are inputs, 0 otherwise
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xlnx,all-outputs-2:
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type: int
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description: |
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1 if all GPIO2s are outputs, 0 otherwise
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xlnx,dout-default-2:
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type: int
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description: |
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Default output value. If n-th bit is 1, GPIO2-n default value is 1.
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xlnx,gpio2-width:
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type: int
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description: |
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Number of GPIO2s supported
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xlnx,tri-default-2:
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type: int
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description: |
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Default tristate register value. If n-th bit is 1, GPIO2-n is an input.
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"#gpio-cells":
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const: 2
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gpio-cells:
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- pin
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- flags
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