46 lines
1.4 KiB
YAML
46 lines
1.4 KiB
YAML
#
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# Copyright (c) 2022, Weidmueller Interface GmbH & Co. KG
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# SPDX-License-Identifier: Apache-2.0
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#
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description: |
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Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller node.
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This GPIO controller is contained in both the Xilinx Zynq-7000 and
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ZynqMP (UltraScale) SoCs. It interfaces both I/O pins of the SoC,
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which can be mapped in the system design tools (MIO pins), or SoC-
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internal signals between the processor system and the programmable
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logic part of the SoC (EMIO pins).
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It is organized in banks, where the number of banks and total number
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of available GPIO pins differs between the two SoC families:
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Zynq-7000 (comp. Zynq-7000 TRM, chap. 14.1.2, p. 381):
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* Bank 0: MIO pins [31:00]
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* Bank 1: MIO pins [53:32] (total: 54 MIO pins)
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* Bank 2: EMIO pins [31:00]
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* Bank 3: EMIO pins [63:32] (total: 64 EMIO pins)
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ZynqMP (UltraScale) (comp. Ultrascale TRM, chap. 27, p. 769):
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* Bank 0: MIO pins [25:00]
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* Bank 1: MIO pins [51:26]
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* Bank 2: MIO pins [77:52] (total: 78 MIO pins, 26 per bank)
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* Bank 3: EMIO pins [31:00]
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* Bank 4: EMIO pins [63:32]
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* Bank 5: EMIO pins [95:64] (total: 96 EMIO pins)
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The controller is interrupt-capable. Certain pins both in the Zynq-
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7000 and the ZynqMP are reserved or at least limited regarding their
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direction.
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compatible: "xlnx,ps-gpio"
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include: base.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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