85 lines
1.6 KiB
C
85 lines
1.6 KiB
C
/*
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* Copyright (c) 2019 Intel Corp.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_X86_MSR_H_
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#define ZEPHYR_INCLUDE_ARCH_X86_MSR_H_
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/*
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* Model specific registers (MSR). Access with z_x86_msr_read/write().
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*/
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#define X86_TIME_STAMP_COUNTER_MSR 0x00000010
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#define X86_SPEC_CTRL_MSR 0x00000048
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#define X86_SPEC_CTRL_MSR_IBRS BIT(0)
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#define X86_SPEC_CTRL_MSR_SSBD BIT(2)
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#define X86_APIC_BASE_MSR 0x0000001b
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#define X86_APIC_BASE_MSR_X2APIC BIT(10)
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#define X86_MTRR_DEF_TYPE_MSR 0x000002ff
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#define X86_MTRR_DEF_TYPE_MSR_ENABLE BIT(11)
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#define X86_X2APIC_BASE_MSR 0x00000800 /* .. thru 0x00000BFF */
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#define X86_EFER_MSR 0xC0000080
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#define X86_EFER_MSR_LME BIT(8)
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#define X86_EFER_MSR_NXE BIT(11)
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#ifndef _ASMLANGUAGE
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* z_x86_msr_write() is shared between 32- and 64-bit implementations, but
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* due to ABI differences with long return values, z_x86_msr_read() is not.
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*/
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static inline void z_x86_msr_write(unsigned int msr, u64_t data)
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{
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u32_t high = data >> 32;
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u32_t low = data & 0xFFFFFFFF;
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__asm__ volatile ("wrmsr" : : "c"(msr), "a"(low), "d"(high));
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}
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#ifdef CONFIG_X86_64
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static inline u64_t z_x86_msr_read(unsigned int msr)
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{
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union {
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struct {
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u32_t lo;
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u32_t hi;
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};
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u64_t value;
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} rv;
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__asm__ volatile ("rdmsr" : "=a" (rv.lo), "=d" (rv.hi) : "c" (msr));
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return rv.value;
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}
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#else
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static inline u64_t z_x86_msr_read(unsigned int msr)
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{
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u64_t ret;
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__asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));
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return ret;
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_X86_MSR_H_ */
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