155 lines
3.6 KiB
C
155 lines
3.6 KiB
C
/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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* Contributors: 2018 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief RISCV specific kernel interface header
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* This header contains the RISCV specific kernel interface. It is
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* included by the generic kernel interface header (arch/cpu.h)
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_ARCH_H_
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#define ZEPHYR_INCLUDE_ARCH_RISCV_ARCH_H_
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#include "exp.h"
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#include <arch/common/sys_io.h>
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#include <arch/common/ffs.h>
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#include <irq.h>
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#include <sw_isr_table.h>
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#include <soc.h>
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#include <generated_dts_board.h>
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/* stacks, for RISCV architecture stack should be 16byte-aligned */
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#define STACK_ALIGN 16
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#ifdef CONFIG_64BIT
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#define RV_OP_LOADREG ld
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#define RV_OP_STOREREG sd
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#define RV_REGSIZE 8
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#define RV_REGSHIFT 3
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#else
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#define RV_OP_LOADREG lw
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#define RV_OP_STOREREG sw
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#define RV_REGSIZE 4
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#define RV_REGSHIFT 2
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#endif
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#ifndef _ASMLANGUAGE
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#include <sys/util.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN)
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#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN)
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/* macros convert value of its argument to a string */
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#define DO_TOSTR(s) #s
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#define TOSTR(s) DO_TOSTR(s)
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/* concatenate the values of the arguments into one */
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#define DO_CONCAT(x, y) x ## y
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#define CONCAT(x, y) DO_CONCAT(x, y)
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/*
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* SOC-specific function to get the IRQ number generating the interrupt.
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* __soc_get_irq returns a bitfield of pending IRQs.
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*/
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extern u32_t __soc_get_irq(void);
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void z_arch_irq_enable(unsigned int irq);
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void z_arch_irq_disable(unsigned int irq);
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int z_arch_irq_is_enabled(unsigned int irq);
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void z_arch_irq_priority_set(unsigned int irq, unsigned int prio);
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void z_irq_spurious(void *unused);
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#if defined(CONFIG_RISCV_HAS_PLIC)
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#define Z_ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
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({ \
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Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
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z_arch_irq_priority_set(irq_p, priority_p); \
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irq_p; \
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})
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#else
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#define Z_ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
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({ \
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Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
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irq_p; \
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})
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#endif
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/*
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* use atomic instruction csrrc to lock global irq
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* csrrc: atomic read and clear bits in CSR register
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*/
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static ALWAYS_INLINE unsigned int z_arch_irq_lock(void)
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{
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unsigned int key;
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ulong_t mstatus;
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__asm__ volatile ("csrrc %0, mstatus, %1"
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: "=r" (mstatus)
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: "r" (SOC_MSTATUS_IEN)
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: "memory");
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key = (mstatus & SOC_MSTATUS_IEN);
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return key;
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}
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/*
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* use atomic instruction csrrs to unlock global irq
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* csrrs: atomic read and set bits in CSR register
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*/
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static ALWAYS_INLINE void z_arch_irq_unlock(unsigned int key)
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{
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ulong_t mstatus;
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__asm__ volatile ("csrrs %0, mstatus, %1"
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: "=r" (mstatus)
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: "r" (key & SOC_MSTATUS_IEN)
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: "memory");
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}
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static ALWAYS_INLINE bool z_arch_irq_unlocked(unsigned int key)
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{
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/* FIXME: looking at z_arch_irq_lock, this should be reducable
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* to just testing that key is nonzero (because it should only
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* have the single bit set). But there is a mask applied to
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* the argument in z_arch_irq_unlock() that has me worried
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* that something elseswhere might try to set a bit? Do it
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* the safe way for now.
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*/
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return (key & SOC_MSTATUS_IEN) == SOC_MSTATUS_IEN;
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}
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static ALWAYS_INLINE void z_arch_nop(void)
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{
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__asm__ volatile("nop");
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}
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extern u32_t z_timer_cycle_get_32(void);
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static inline u32_t z_arch_k_cycle_get_32(void)
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{
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return z_timer_cycle_get_32();
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /*_ASMLANGUAGE */
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#if defined(CONFIG_SOC_FAMILY_RISCV_PRIVILEGE)
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#include <arch/riscv/riscv-privilege/asm_inline.h>
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#endif
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#endif
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