39 lines
1.1 KiB
C
39 lines
1.1 KiB
C
/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/types.h>
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#include <stdio.h>
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#include <xtensa_api.h>
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#include <kernel_arch_data.h>
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#include <misc/__assert.h>
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/*
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* @internal
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*
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* @brief Set an interrupt's priority
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*
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* The priority is verified if ASSERT_ON is enabled.
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*
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* The priority is verified if ASSERT_ON is enabled. The maximum number of
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* priority levels is a little complex, as there are some hardware priority
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* levels which are reserved: three for various types of exceptions, and
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* possibly one additional to support zero latency interrupts.
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*
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* Valid values are from 1 to 6. Interrupts of priority 1 are not masked when
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* interrupts are locked system-wide, so care must be taken when using them.
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* ISR installed with priority 0 interrupts cannot make kernel calls.
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*
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* @return N/A
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*/
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void _irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
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{
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__ASSERT(prio < XCHAL_EXCM_LEVEL + 1,
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"invalid priority %d! values must be less than %d\n",
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prio, XCHAL_EXCM_LEVEL + 1);
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/* TODO: Write code to set priority if this is ever possible on
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* Xtensa
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*/
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}
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